MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 767

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
rs
rs
w
Bits 14:2 Reserved
w
Bits 1:0 MPSIZ: Maximum packet size
OTG_FS device endpoint-x control register (OTG_FS_DOEPCTLx) (x = 1..3,
where x = Endpoint_number)
Address offset for OUT endpoints: 0xB00 + (Endpoint_number × 0x20)
Reset value: 0x0000 0000
The application uses this register to control the behavior of each logical endpoint other than
endpoint 0.
Bit 17 NAKSTS: NAK status
Bit 16 Reserved
Bit 15 USBAEP: USB active endpoint
Bit 31 EPENA: Endpoint enable
w
w
Indicates the following:
When either the application or the core sets this bit, the core stops receiving data, even if there
is space in the RxFIFO to accommodate the incoming packet. Irrespective of this bit’s setting,
the core always responds to SETUP data packets with an ACK handshake.
This bit is always set to 1, indicating that a control endpoint 0 is always active in all
configurations and interfaces.
The maximum packet size for control OUT endpoint 0 is the same as what is programmed in
control IN endpoint 0.
Applies to IN and OUT endpoints.
The application sets this bit to start transmitting data on an endpoint.
The core clears this bit before setting any of the following interrupts on this endpoint:
– SETUP phase done
– Endpoint disabled
– Transfer completed
0: The core is transmitting non-NAK handshakes based on the FIFO status.
1: The core is transmitting NAK handshakes on this endpoint.
00: 64 bytes
01: 32 bytes
10: 16 bytes
11: 8 bytes
Reserved
rw/
rs
rw rw rw
Doc ID 13902 Rev 9
r
r
rw
Reserved
USB on-the-go full-speed (OTG_FS)
rw rw rw rw rw rw rw rw rw rw rw
9
8
7
6
MPSIZ
5
4
3
2
767/995
1
0