MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 593

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
23.3.2
23.3.3
SPI slave mode
In slave configuration, the serial clock is received on the SCK pin from the master device.
The value set in the BR[2:0] bits in the SPI_CR1 register, does not affect the data transfer
rate.
Procedure
1.
2.
3.
4.
5.
In this configuration the MOSI pin is a data input and the MISO pin is a data output.
Transmit sequence
The data byte is parallel-loaded into the Tx buffer during a write cycle.
The transmit sequence begins when the slave device receives the clock signal and the most
significant bit of the data on its MOSI pin. The remaining bits (the 7 bits in 8-bit data frame
format, and the 15 bits in 16-bit data frame format) are loaded into the shift-register. The
TXE flag in the SPI_SR register is set on the transfer of data from the Tx Buffer to the shift
register and an interrupt is generated if the TXEIE bit in the SPI_CR2 register is set.
Receive sequence
For the receiver, when data transfer is complete:
●
●
After the last sampling clock edge the RXNE bit is set, a copy of the data byte received in
the shift register is moved to the Rx buffer. When the SPI_DR register is read, the SPI
peripheral returns this buffered value.
Clearing of the RXNE bit is performed by reading the SPI_DR register.
SPI master mode
In the master configuration, the serial clock is generated on the SCK pin.
Set the DFF bit to define 8- or 16-bit data frame format
Select the CPOL and CPHA bits to define one of the four relationships between the
data transfer and the serial clock (see
and CPHA bits must be configured in the same way in the slave device and the master
device.
The frame format (MSB-first or LSB-first depending on the value of the LSBFIRST bit in
the SPI_CR1 register) must be the same as the master device.
In Hardware mode (refer to
NSS pin must be connected to a low level signal during the complete byte transmit
sequence. In Software mode, set the SSM bit and clear the SSI bit in the SPI_CR1
register.
Clear the MSTR bit and set the SPE bit (both in the SPI_CR1 register) to assign the
pins to alternate functions.
The Data in shift register is transferred to Rx Buffer and the RXNE flag (SPI_SR
register) is set
An Interrupt is generated if the RXNEIE bit is set in the SPI_CR2 register.
Doc ID 13902 Rev 9
Slave select (NSS) pin management on page
Figure
210). For correct data transfer, the CPOL
Serial peripheral interface (SPI)
590), the
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