MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 316

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Advanced-control timers (TIM1&TIM8)
13.4.19
316/995
15
Reserved
Res.
14
Bits 15:13 Reserved, always read as 0
Bits 12:8 DBL[4:0]: DMA burst length
Bits 7:0 DTG[7:0]: Dead-time generator setup
Bits 7:5 Reserved, always read as 0
TIM1&TIM8 DMA control register (TIMx_DCR)
Address offset: 0x48
Reset value: 0x0000
13
Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed
This 5-bit vector defines the length of DMA transfers (the timer recognizes a burst transfer
when a read or a write access is done to the TIMx_DMAR address), i.e. the number of
transfers. Transfers can be in half-words or in bytes (see example below).
00000: 1 transfer,
00001: 2 transfers,
00010: 3 transfers,
...
10001: 18 transfers.
Example: Let us consider the following transfer: DBL = 7 bytes & DBA = TIM2_CR1.
– If DBL = 7 bytes and DBA = TIM2_CR1 represents the address of the byte to be transferred,
In this example, 7 bytes are added to (TIMx_CR1 address) + DBA, which gives us the address
from/to which the data will be copied. In this case, the transfer is done to 7 registers starting
from the following address: (TIMx_CR1 address) + DBA
According to the configuration of the DMA Data Size, several cases may occur:
– If you configure the DMA Data Size in half-words, 16-bit data will be transferred to each of
– If you configure the DMA Data Size in bytes, the data will aslo be transferred to 7 registers:
This bit-field defines the duration of the dead-time inserted between the complementary
outputs. DT correspond to this duration.
DTG[7:5]=0xx => DT=DTG[7:0]x t
DTG[7:5]=10x => DT=(64+DTG[5:0])xt
DTG[7:5]=110 => DT=(32+DTG[4:0])xt
DTG[7:5]=111 => DT=(32+DTG[4:0])xt
Example if T
0 to 15875 ns by 125 ns steps,
16 us to 31750 ns by 250 ns steps,
32 us to 63us by 1 us steps,
64 us to 126 us by 2 us steps
the address of the transfer should be given by the following equation:
(TIMx_CR1 address) + DBA + (DMA index), where DMA index = DBL
the 7 registers.
the first register will contain the first MSB byte, the second register, the first LSB byte and so
on. So with the transfer Timer, you also have to specify the size of data transferred by DMA.
12
rw
(LOCK bits in TIMx_BDTR register).
11
rw
DTS
DBL[4:0]
10
rw
=125ns (8MHz), dead-time possible values are:
rw
9
Doc ID 13902 Rev 9
rw
8
dtg
with t
7
dtg
dtg
dtg
Reserved
with T
with T
with T
dtg
Res.
=t
6
DTS
dtg
dtg
dtg
.
=2xt
=8xt
=16xt
5
DTS
DTS
DTS
.
.
rw
4
.
rw
3
DBA[4:0]
rw
2
rw
1
RM0008
rw
0