MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 590

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Serial peripheral interface (SPI)
590/995
Figure 208. Single master/ single slave application
1. Here, the NSS pin is configured as an input.
The MOSI pins are connected together and the MISO pins are connected together. In this
way data is transferred serially between master and slave (most significant bit first).
The communication is always initiated by the master. When the master device transmits
data to a slave device via the MOSI pin, the slave device responds via the MISO pin. This
implies full-duplex communication with both data out and data in synchronized with the
same clock signal (which is provided by the master device via the SCK pin).
Slave select (NSS) pin management
There are two NSS modes:
●
●
Figure 209. Hardware/software slave select management
Software NSS mode: this mode is enabled by setting the SSM bit in the SPI_CR1
register (see
application uses and the internal NSS signal level is driven by writing to the SSI bit in
the SPI_CR1 register.
Hardware NSS mode: there are two cases:
–
–
NSS output is enabled: when the STM32F20xxx is operating as a Master and the
NSS output is enabled through the SSOE bit in the SPI_CR2 register, the NSS pin
is driven low and all the NSS pins of devices connected to the Master NSS pin see
a low level and become slaves when they are configured in NSS hardware mode.
When an SPI wants to broadcast a message, it has to pull NSS low to inform all
others that there is now a master for the bus. If it fails to pull NSS low, this means
that there is another master communicating, and a Hard Fault error occurs.
NSS output is disabled: the multimaster capability is allowed.
MSBit
8-bit shift register
SPI clock
generator
Master
Figure
LSBit
NSS external pin
209). In this mode, the external NSS pin is free for other
Doc ID 13902 Rev 9
SSI bit
NSS
MOSI
SCK
MISO
(1)
SSM bit
V
DD
1
0
NSS Internal
NSS
MISO
MOSI
SCK
(1)
Not used if NSS is managed
by software
8-bit shift register
MSBit
Slave
LSBit
ai14746
RM0008
ai14745