MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 841

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
Table 188. Ethernet pin configuration (continued)
27.4
27.4.1
ETH_MII_RXD2
ETH_MII_RXD3
MAC signals
Ethernet functional description: SMI, MII and RMII
The Ethernet peripheral consists of a MAC 802.3 (media access control) with a dedicated
DMA controller. It supports both default media-independent interface (MII) and reduced
media-independent interface (RMII) through one selection bit (refer to AFIO_MAPR
register).
The DMA controller interfaces with the Core and memories through the AHB Master and
Slave interfaces. The AHB Master Interface controls data transfers while the AHB Slave
interface accesses Control and Status Registers (CSR) space.
The Transmit FIFO (Tx FIFO) buffers data read from system memory by the DMA before
transmission by the MAC Core. Similarly, the Receive FIFO (Rx FIFO) stores the Ethernet
frames received from the line until they are transferred to system memory by the DMA.
The Ethernet peripheral also includes an SMI to communicate with external PHY. A set of
configuration registers permit the user to select the wanted mode and features for the MAC
and the DMA controller.
Figure 284. ETH block diagram
Station management interface: SMI
The station management interface (SMI) allows the application to access any PHY registers
through a 2-wire clock and data lines. The interface supports accessing up to 32 PHYs.
-
-
MII default MII remap RMII default RMII remap
DMA
RXD2
RXD3
Ethernet (ETH): media access control (MAC) with DMA controller
Registers
& Status
Control
DMA
FIFO
DMA
Doc ID 13902 Rev 9
TX
Operation
-
-
Register
Mode
FIFO
DMA
RX
-
-
MAC 802.3
Access
Control
Media
Registers
Control
MAC
PD11
PD12
Pin
Interface
Floating input (reset state)
Floating input (reset state)
MII
RMII
Pin configuration
MDIO
MDC
Select
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