MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 400

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Independent watchdog (IWDG)
17.3.1
17.3.2
17.3.3
Note:
Table 81.
1. These timings are given for a 40 kHz clock but the microcontroller’s internal RC frequency can vary from 30 to 60 kHz.
400/995
Prescaler divider
Moreover, given an exact RC oscillator frequency, the exact timings still depend on the phasing of the APB interface clock
versus the LSI clock so that there is always a full RC period of uncertainty.
/128
/256
/16
/32
/64
/4
/8
Hardware watchdog
If the “Hardware watchdog” feature is enabled through the device option bits, the watchdog
is automatically enabled at power-on, and will generate a reset unless the Key register is
written by the software before the counter reaches end of count.
Register access protection
Write access to the IWDG_PR and IWDG_RLR registers is protected. To modify them, you
must first write the code 0x5555 in the IWDG_KR register. A write access to this register
with a different value will break the sequence and register access will be protected again.
This implies that it is the case of the reload operation (writing 0xAAAA).
A status register is available to indicate that an update of the prescaler or the down-counter
reload value is on going.
Debug mode
When the microcontroller enters debug mode (Cortex-M3 core halted), the IWDG counter
either continues to work normally or stops, depending on DBG_IWDG_STOP configuration
bit in DBG module. For more details, refer to
watchdog, bxCAN and I
Figure 158. Independent watchdog block diagram
The watchdog function is implemented in the V
Stop and Standby modes.
Watchdog timeout period (with 40 kHz input clock)Min/max IWDG timeout
period at 32 kHz (LSI)
(40 kHz)
LSI
Prescaler register
1.8 V voltage domain
V
DD
PR[2:0] bits
IWDG_PR
prescaler
6 (or 7)
voltage domain
8-bit
0
1
2
3
4
5
Min timeout (ms) RL[11:0]= 0x000
Status register
2
(1)
IWDG_SR
C.
Doc ID 13902 Rev 9
0.1
0.2
0.4
0.8
1.6
3.2
6.4
12-bit downcounter
12-bit reload value
Reload register
IWDG_RLR
Section 29.16.2: Debug support for timers,
DD
voltage domain that is still functional in
Max timeout (ms) RL[11:0]= 0xFFF
IWDG RESET
Key register
IWDG_KR
13107.2
26214.4
1638.4
3276.8
6553.6
409.6
819.2
RM0008