MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 747

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bits 31:16 Reserved
Bits 31:19 Reserved
Bits 18:17 PSPD: Port speed
Bits 15:0 HAINTM: Channel interrupt mask
OTG_FS host all channels interrupt mask register (OTG_FS_HAINTMSK)
Address offset: 0x418
Reset value: 0x0000 0000
The host all channel interrupt mask register works with the host all channel interrupt register
to interrupt the application when an event occurs on a channel. There is one interrupt mask
bit per channel, up to a maximum of 16 bits.
OTG_FS host port control and status register (OTG_FS_HPRT)
Address offset: 0x440
Reset value: 0x0000 0000
This register is available only in Host mode. Currently, the OTG Host supports only one port.
A single register holds USB port-related information such as USB reset, enable, suspend,
resume, connect status, and test mode for each port. It is shown in
bits in this register can trigger an interrupt to the application through the Host port interrupt
bit of the core interrupt register (HPRTINT bit in OTG_FS_GINTSTS). On a Port Interrupt,
the application must read this register and clear the bit that caused the interrupt. For the
rc_w1 bits, the application must write a 1 to the bit to clear the interrupt.
Reserved
One bit per channel: Bit 0 for channel 0, bit 15 for channel 15
Indicates the speed of the device attached to this port.
0: Masked interrupt
1: Unmasked interrupt
01: Full speed
10: Low speed
11: Reserved
Reserved
PSPD
Doc ID 13902 Rev 9
r
r
rw rw rw rw rw
PTCTL
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
USB on-the-go full-speed (OTG_FS)
r
r
9
9
rw
HAINTM
8
8
rs
7
7
Figure
rw
6
6
rc_
w1
5
5
268. The rc_w1
4
4
r
rc_
w1
3
3
rc_
w0
2
2
747/995
rc_
w1
1
1
0
r
0