MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 414

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Flexible static memory controller (FSMC)
19.5
19.5.1
414/995
NOR Flash/PSRAM controller
The FSMC generates the appropriate signal timings to drive the following types of
memories:
●
●
●
The FSMC outputs a unique chip select signal NE[4:1] per bank. All the other signals
(addresses, data and control) are shared.
For synchronous accesses, the FSMC issues the clock (CLK) to the selected external
device. This clock is a submultiple of the HCLK clock. The size of each bank is fixed and
equal to 64 Mbytes.
Each bank is configured by means of dedicated registers (see
The programmable memory parameters include access timings (see
for wrap and wait management (for PSRAM and NOR Flash accessed in burst mode).
Table 88.
External memory interface signals
Table
Flash and PSRAM.
Address
setup
Address hold
Data setup
Bust turn
Clock divide
ratio
Data latency
Parameter
Asynchronous SRAM and ROM
–
–
–
PSRAM (Cellular RAM)
–
–
NOR Flash
–
–
89,
8-bit
16-bit
32-bit
Asynchronous mode
Burst mode
Asynchronous mode or burst mode
Multiplexed or nonmultiplexed
Table 90
Programmable NOR/PSRAM access parameters
Duration of the address
setup phase
Duration of the address hold
phase
Duration of the data setup
phase
Duration of the bus
turnaround phase
Number of AHB clock cycles
(HCLK) to build one memory
clock cycle (CLK)
Number of clock cycles to
issue to the memory before
the first data of the burst
and
Table 91
Function
Doc ID 13902 Rev 9
list the signals that are typically used to interface NOR
Asynchronous
Asynchronous,
muxed I/Os
Asynchronous
Asynchronous and
synchronous read
Synchronous
Synchronous
Access mode
AHB clock cycle
(HCLK)
AHB clock cycle
(HCLK)
AHB clock cycle
(HCLK)
AHB clock cycle
(HCLK)
AHB clock cycle
(HCLK)
Memory clock
cycle (CLK)
Section
Unit
Table
19.6.7).
88) and support
Min.
1
2
2
1
1
2
RM0008
Max.
256
16
16
16
16
17