MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 437

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
Bits 5:4 MWID: Memory databus width.
Bits 3:2 MTYP: Memory type.
Bit 10 WRAPMOD: Wrapped burst mode support.
Bit 9 WAITPOL: Wait signal polarity bit.
Bit 8 BURSTEN: Burst enable bit.
Bit 7
Bit 6 FACCEN: Flash access enable
Bit 1 MUXEN: Address/data multiplexing enable bit.
Bit 0 MBKEN: Memory bank enable bit.
Defines whether the controller will or not split an AHB burst wrap access into two linear accesses.
Valid only when accessing memories in burst mode
0: Direct wrapped burst is not enabled (default after reset),
1: Direct wrapped burst is enabled.
Defines the polarity of the wait signal from memory. Valid only when accessing the memory in burst
mode:
0: NWAIT active low (default after reset),
1: NWAIT active high.
Enables the burst access mode for the memory. Valid only with synchronous burst memories:
0: Burst access mode disabled (default after reset)
1: Burst access mode enable
Reserved.
Enables NOR Flash memory access operations.
0: Corresponding NOR Flash memory access is disabled
1: Corresponding NOR Flash memory access is enabled (default after reset)
Defines the external memory device width, valid for all type of memories.
00: 8 bits,
01: 16 bits (default after reset),
10: reserved, do not use,
11: reserved, do not use.
Defines the type of external memory attached to the corresponding memory bank:
00: SRAM, ROM (default after reset for Bank 2...4)
01: PSRAM (Cellular RAM: CRAM)
10: NOR Flash(default after reset for Bank 1)
11: reserved
When this bit is set, the address and data values are multiplexed on the databus, valid only with
NOR and PSRAM memories:
0: Address/Data nonmultiplexed
1: Address/Data multiplexed on databus (default after reset)
Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a
disabled bank causes an ERROR on AHB bus.
0: Corresponding memory bank is disabled
1: Corresponding memory bank is enabled
Doc ID 13902 Rev 9
Flexible static memory controller (FSMC)
437/995