MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 932

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Ethernet (ETH): media access control (MAC) with DMA controller
27.8.4
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Reserved
Bits 31:26 Reserved
Bits 31:0 TTSL: Target time stamp low
Ethernet PTP target time low register (ETH_PTPTTLR)
Address offset: 0x0720
Reset value: 0x0000 0000
This register contains the lower 32 bits of time to be compared with the system time for
interrupt event generation.
DMA register description
This section defines the bits for each DMA register. Non-32 bit accesses are allowed as long
as the address is word-aligned.
Ethernet DMA bus mode register (ETH_DMABMR)
Address offset: 0x1000
Reset value: 0x0000 2101
The bus mode register establishes the bus operating modes for the DMA.
Bit 25 AAB: Address-aligned beats
Bit 24 FPM: 4xPBL mode
Bit 23 USP: Use separate PBL
This register stores the time in (signed) nanoseconds. When the value of the time stamp
matches or exceeds both Target time stamp registers, the MAC, if enabled, generates an
interrupt.
When this bit is set high and the FB bit equals 1, the AHB interface generates all bursts aligned
to the start address LS bits. If the FB bit equals 0, the first burst (accessing the data buffer’s
start address) is not aligned, but subsequent bursts are aligned to the address.
When set high, this bit multiplies the PBL value programmed (bits [22:17] and bits [13:8]) four
times. Thus the DMA transfers data in a maximum of 4, 8, 16, 32, 64 and 128 beats depending
on the PBL value.
When set high, it configures the RxDMA to use the value configured in bits [22:17] as PBL
while the PBL value in bits [13:8] is applicable to TxDMA operations only. When this bit is
cleared, the PBL value in bits [13:8] is applicable for both DMA engines.
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RDP
Doc ID 13902 Rev 9
TTSL
RTPR
PBL
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8
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7
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6
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DSL
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4
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3
RM0008
2
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1
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rs
0
0