MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 191

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
10.4
Note:
10.4.1
TEIF4
Bits 27, 23, 19, 15,
Bits 26, 22, 18, 14,
Bits 25, 21, 17, 13,
Bits 24, 20, 16, 12,
31
15
r
HTIF4
30
14
Bits 31:28
Reserved
r
11, 7, 3
10, 6, 2
9, 5, 1
8, 4, 0
DMA registers
Refer to
In the following registers, all bits relative to channel6 and channel7 are not relevant for
DMA2 since it has only 5 channels.
DMA interrupt status register (DMA_ISR)
Address offset: 0x00
Reset value: 0x0000 0000
TCIF4
29
13
r
TEIFx: Channel x transfer error flag (x = 1 ..7)
HTIFx: Channel x half transfer flag (x = 1 ..7)
TCIFx: Channel x transfer complete flag (x = 1 ..7)
GIFx: Channel x global interrupt flag (x = 1 ..7)
GIF4
28
12
Reserved, always read as 0.
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_IFCR register.
0: No transfer error (TE) on channel x
1: A transfer error (TE) occurred on channel x
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_IFCR register.
0: No half transfer (HT) event on channel x
1: A half transfer (HT) event occurred on channel x
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_IFCR register.
0: No transfer complete (TC) event on channel x
1: A transfer complete (TC) event occurred on channel x
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_IFCR register.
0: No TE, HT or TC event on channel x
1: A TE, HT or TC event occurred on channel x
Section 1.1 on page 37
r
TEIF7
TEIF3
27
11
r
r
HTIF7
HTIF3
26
10
r
r
TCIF7
TCIF3
25
9
r
r
Doc ID 13902 Rev 9
for a list of abbreviations used in the register descriptions.
GIF7
GIF3
24
8
r
r
TEIF6
TEIF2
23
7
r
r
HTIF6
HTIF2
22
6
r
r
TCIF6
TCIF2
21
5
r
r
GIF6
GIF2
20
4
r
r
TEIF5
TEIF1
19
DMA controller (DMA)
3
r
r
HTIF5
HTIF1
18
2
r
r
TCIF5
TCIF1
17
1
r
r
191/995
GIF5
GIF1
16
0
r
r