MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 616

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Serial peripheral interface (SPI)
23.5.2
616/995
15
Bits 15:8 Reserved. Forced to 0 by hardware.
Bits 4:3 Reserved. Forced to 0 by hardware.
Bit 7 TXEIE: Tx buffer empty interrupt enable
Bit 6 RXNEIE: RX buffer not empty interrupt enable
Bit 5 ERRIE: Error interrupt enable
14
SPI control register 2 (SPI_CR2)
Address offset: 0x04
Reset value: 0x0000
Note: To function correctly, the TXEIE and TXDMAEN bits should not be set at the same time.
Note: To function correctly, the RXNEIE and RXDMAEN bits should not be set at the same time.
Bit 2 MSTR: Master selection
Bit 0 CPHA: Clock phase
Bit1 CPOL: Clock polarity
13
0: TXE interrupt masked
1: TXE interrupt not masked. Used to generate an interrupt request when the TXE flag is set.
0: RXNE interrupt masked
1: RXNE interrupt not masked. Used to generate an interrupt request when the RXNE flag is set.
This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR,
MODF in SPI mode and UDR, OVR in I
0: Error interrupt is masked
1: Error interrupt is enabled.
Note: This bit should not be changed when communication is ongoing.
Note: This bit should not be changed when communication is ongoing.
Note: This bit should not be changed when communication is ongoing.
12
0: Slave configuration
1: Master configuration
0: CK to 0 when idle
1: CK to 1 when idle
0: The first clock transition is the first data capture edge
1: The second clock transition is the first data capture edge
Reserved
Res.
Not used in I
Not used in I
Not used in I
11
10
2
2
2
S mode
S mode
S mode
9
Doc ID 13902 Rev 9
8
2
S mode).
TXEIE
rw
7
RXNE
rw
IE
6
ERRIE
rw
5
4
reserved
Res.
3
SSOE
rw
2
TXDMA
EN
rw
1
RM0008
RXDMA
EN
rw
0