MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 381

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
15.3.4
15.4
15.4.1
15
14
Bits 15:8 Reserved, always read as 0
Bits 6:4 Reserved, always read as 0
Figure 154. Control circuit in normal mode, internal clock divided by 1
Debug mode
When the microcontroller enters the debug mode (Cortex-M3 core - halted), the TIMx
counter either continues to work normally or stops, depending on the DBG_TIMx_STOP
configuration bit in the DBG module. For more details, refer to
support for timers, watchdog, bxCAN and I
TIM6&TIM7 registers
Refer to
TIM6&TIM7 control register 1 (TIMx_CR1)
Address offset: 0x00
Reset value: 0x0000
Bit 7 ARPE: Auto-reload preload enable
Bit 3 OPM: One-pulse mode
13
Counter clock = CK_CNT = CK_PSC
Section 1.1 on page 37
0: TIMx_ARR register is not buffered.
1: TIMx_ARR register is buffered.
0: Counter is not stopped at update event
1: Counter stops counting at the next update event (clearing the CEN bit).
12
Reserved
11
10
CEN=CNT_EN
Counter register
CNT_INIT
CK_INT
9
UG
Doc ID 13902 Rev 9
for a list of abbreviations used in register descriptions.
8
31
ARPE
rw
7
32 33 34 35 36
2
C.
6
Reserved
5
00
01 02 03 04 05 06 07
4
Section 29.16.2: Debug
Basic timers (TIM6&TIM7)
OPM
rw
3
URS
rw
2
UDIS
rw
1
381/995
CEN
rw
0