MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 356

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

General-purpose timer (TIMx)
14.4.2
356/995
15
14
Bits 15:8 Reserved, always read as 0.
TIMx control register 2 (TIMx_CR2)
Address offset: 0x04
Reset value: 0x0000
Bit 7 TI1S: TI1 selection
Bit 2 URS: Update request source
Bit 1 UDIS: Update disable
Bit 0 CEN: Counter enable
13
Note: External clock, gated mode and encoder mode can work only if the CEN bit has been
CEN is cleared automatically in one pulse mode, when an update event occurs.
0: The TIMx_CH1 pin is connected to TI1 input.
1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination)
See also
This bit is set and cleared by software to select the UEV event sources.
0: Any of the following events generate an update interrupt or DMA request if enabled.
These events can be:
1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled.
This bit is set and cleared by software to enable/disable UEV event generation.
0: UEV enabled. The Update (UEV) event is generated by one of the following events:
Buffered registers are then loaded with their preload values.
1: UEV disabled. The Update event is not generated, shadow registers keep their value
(ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is
set or if a hardware reset is received from the slave mode controller.
0: Counter disabled
1: Counter enabled
12
Reserved
–
–
–
–
–
–
previously set by software. However trigger mode can set the CEN bit automatically by
hardware.
11
Counter overflow/underflow
Setting the UG bit
Update generation through the slave mode controller
Counter overflow/underflow
Setting the UG bit
Update generation through the slave mode controller
Section 13.3.18: Interfacing with Hall sensors on page 288
10
9
Doc ID 13902 Rev 9
8
TI1S
rw
7
rw
6
MMS[2:0]
rw
5
rw
4
CCDS
rw
3
2
Reserved
1
RM0008
0