MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 712

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

USB on-the-go full-speed (OTG_FS)
26.10
26.10.1
712/995
Peripheral FIFO architecture
Figure 266. Device-mode FIFO address mapping and AHB FIFO access mapping
Peripheral Rx FIFO
The OTG peripheral uses a single receive FIFO that receives the data directed to all OUT
endpoints. Received packets are stacked back-to-back until free space is available in the
Rx-FIFO. The status of the received packet (which contains the OUT endpoint destination
number, the byte count, the data PID and the validity of the received data) is also stored by
the PFC on top of the data payload . When no more space is available, host transactions are
NACKed and an interrupt is received on the addressed endpoint. The size of the receive
FIFO is configured in the receive FIFO Size register (GRXFSIZ).
The single receive FIFO architecture makes it more efficient for the USB peripheral to fill in
the receive RAM buffer
●
●
The application keeps receiving the Rx-FIFO non-empty interrupt (RXFLVL bit in
OTG_FS_GINTSTS) as long as there is at least one packet available for download. It reads
the packet information from the receive status read and pop register (GRXSTSP) and finally
pops data off the receive FIFO by reading from the endpoint-related pop address.
Any OUT endpoint DFIFO pop
all OUT endpoints share the same RAM buffer (shared FIFO)
the OTG FS Core can fill in the receive FIFO up to the limit for any host sequence of
OUT tokens
IN endpoint Tx FIFO #0
IN endpoint Tx FIFO #n
IN endpoint Tx FIFO #1
DFIFO push access
DFIFO push access
DFIFO push access
access from AHB
from AHB
from AHB
from AHB
MAC push
MAC pop
MAC pop
MAC pop
Doc ID 13902 Rev 9
Rx FIFO control
Dedicated Tx
FIFO #n control
(optional)
Dedicated Tx
FIFO #1 control
(optional)
Dedicated Tx
FIFO #0 control
(optional)
. .
.
Tx FIFO #1 packet
Tx FIFO #0 packet
Tx FIFO #n
Single data
Rx packets
packet
FIFO
. .
.
DIEPTXF2[31:16]
DIEPTXFx[15:0]
DIEPTXF1[31:16]
DIEPTXF1[15:0]
GNPTXFSIZ[31:16]
GNPTXFSIZ[15:0]
GRXFSIZ[31:16]
A1 = 0
DIEPTXF2[15:0]
. .
.
(Rx start
address
fixed to 0)
RM0008
ai15611