MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 907

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
Bits 21:20 Reserved
Bits 19:17 IFG: Interframe gap
Bit 22 JD: Jabber disable
Bit 16 CSD: Carrier sense disable
Bit 15 Reserved
Bit 14 FES: Fast Ethernet speed
Bit 13 ROD: Receive own disable
Bit 12 LM: Loopback mode
Bit 11 DM: Duplex mode
Bit 10 IPCO: IPv4 checksum offload
When this bit is set, the MAC disables the jabber timer on the transmitter, and can transfer
frames of up to 16 384 bytes.
When this bit is reset, the MAC cuts off the transmitter if the application sends out more than
2 048 bytes of data during transmission.
These bits control the minimum interframe gap between frames during transmission.
Note: In Half-duplex mode, the minimum IFG can be configured for 64 bit times (IFG = 100)
When set high, this bit makes the MAC transmitter ignore the MII CRS signal during frame
transmission in Half-duplex mode. No error is generated due to Loss of Carrier or No Carrier
during such transmission.
When this bit is low, the MAC transmitter generates such errors due to Carrier Sense and even
aborts the transmissions.
Indicates the speed in Fast Ethernet (MII) mode:
When this bit is set, the MAC disables the reception of frames in Half-duplex mode.
When this bit is reset, the MAC receives all packets that are given by the PHY while
transmitting.
This bit is not applicable if the MAC is operating in Full-duplex mode.
When this bit is set, the MAC operates in loopback mode at the MII. The MII receive clock
input (RX_CLK) is required for the loopback to work properly, as the transmit clock is not
looped-back internally.
When this bit is set, the MAC operates in a Full-duplex mode where it can transmit and receive
simultaneously.
When set, this bit enables IPv4 checksum checking for received frame payloads'
TCP/UDP/ICMP headers. When this bit is reset, the checksum offload function in the receiver
is disabled and the corresponding PCE and IP HCE status bits (see
are always cleared.
000: 96 bit times
001: 88 bit times
010: 80 bit times
….
111: 40 bit times
0: 10 Mbit/s
1: 100 Mbit/s
only. Lower values are not considered.
Ethernet (ETH): media access control (MAC) with DMA controller
Doc ID 13902 Rev 9
Table 193 on page
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