MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 666
MCBSTM32EXL
Manufacturer Part Number
MCBSTM32EXL
Description
BOARD EVALUATION FOR STM32F103ZE
Manufacturer
Keil
Specifications of MCBSTM32EXL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Universal synchronous asynchronous receiver transmitter (USART)
Note:
25.3.5
666/995
1
2
The nearest real number is 0d16 = 0x10 => overflow of DIV_frac[3:0] => carry must be
added up to the mantissa
DIV_Mantissa = mantissa (0d50.990 + carry) = 0d51 = 0x33
Then, USART_BRR = 0x330 hence USARTDIV = 0d51.000
Table 174. Error calculation for programmed baud rates
The lower the CPU clock the lower will be the accuracy for a particular Baud rate. The upper
limit of the achievable baud rate can be fixed with this data.
Only USART1 is clocked with PCLK2 (72 MHz Max). Other USARTs are clocked with
PCLK1 (36 MHz Max).
USART receiver’s tolerance to clock deviation
The USART’s asynchronous receiver works correctly only if the total clock system deviation
is smaller than the USART receiver’s tolerance. The causes which contribute to the total
deviation are:
●
●
●
●
DTRA + DQUANT + DREC + DTCL < USART receiver’s tolerance
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
S.No
Baud rate
DTRA: Deviation due to the transmitter error (which also includes the deviation of the
transmitter’s local oscillator)
DQUANT: Error due to the baud rate quantization of the receiver
DREC: Deviation of the receiver’s local oscillator
DTCL: Deviation due to the transmission line (generally due to the transceivers which
can introduce an asymmetry between the low-to-high transition timing and the high-to-
low transition timing)
2.4
9.6
19.2
57.6
115.2 115.384
230.4 230.769
460.8 461.538
921.6 923.076
2250
4500
Kbps
in
2.400
9.600
2250
NA
19.2
57.6
Actual
234.375
Rate register
937.5
117.1875
39.0625
19.5
9.75
4.875
2.4375
1
NA
programmed
in the Baud
Value
f
PCLK
Doc ID 13902 Rev 9
= 36 MHz
0%
0%
0%
0%
0.15%
0.16%
0.16%
0.16%
0%
NA
/Desired B.Rate
Desired)B.Rate
=(Calculated -
% Error
2.4
9.6
19.2
57.6
115.2
230.769 19.5
461.538 9.75
923.076 4.875
2250
4500
Actual
1875
468.75
234.375
78.125
39.0625
2
1
f
PCLK
programmed
Rate register
in the Baud
Value
= 72 MHz
0%
0%
0%
0.%
0%
0.16%
0.16%
0.16%
0%
0%
RM0008
% Error
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