MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 449

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
FIFO status and interrupt register 2..4 (FSMC_SR2..4)
Address offset: 0xA000 0000 + 0x44 + 0x20 * (x-1), x = 2..4
Reset value: 0x0000 0040
This register contains information about FIFO status and interrupt. The FSMC has a FIFO
that is used when writing to memories to store up to16 words of data from the AHB.
This is used to quickly write to the AHB and free it for transactions to peripherals other than
the FSMC, while the FSMC is draining its FIFO into the memory. This register has one of its
bits that indicates the status of the FIFO, for ECC purposes.
The ECC is calculated while the data are written to the memory, so in order to read the
correct ECC the software must wait until the FIFO is empty.
Bit 6 FEMPT: FIFO empty.
Bit 5 IFEN: Interrupt falling edge detection enable bit
Bit 4 ILEN: Interrupt high-level detection enable bit
Bit 3 IREN: Interrupt rising edge detection enable bit
Bit 2 PBKEN: PC Card/NAND Flash memory bank enable bit.
Bit 1 PWAITEN: Wait feature enable bit.
Bit 0
Note: For a PC Card, when the wait feature is enabled, the MEMWAITx/ATTWAITx/IOWAITx
Read-only bit that provides the status of the FIFO
0: FIFO not empty
1: FIFO empty
0: Interrupt falling edge detection request disabled
1: Interrupt falling edge detection request enabled
0: Interrupt high-level detection request disabled
1: Interrupt high-level detection request enabled
0: Interrupt rising edge detection request disabled
1: Interrupt rising edge detection request enabled
Enables the memory bank. Accessing a disabled memory bank causes an ERROR on AHB
bus
0: Corresponding memory bank is disabled (default after reset)
1: Corresponding memory bank is enabled
Enables the Wait feature for the PC Card/NAND Flash memory bank:
0: disabled
1: enabled
Reserved.
bits must be programmed to a value higher than t
t
v(IORDY-NOE)
is the maximum time taken by NWAIT to go low once NOE is low.
Doc ID 13902 Rev 9
Flexible static memory controller (FSMC)
v(IORDY-NOE)
9
8
7
/T
HCLK
6
r
rw rw rw rw rw rw
5
+ 4, where
4
3
2
449/995
1
0