MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 643

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
24.6.2
15
Reserved
14
Bits 15:13 Reserved, forced by hardware to 0.
Control register 2 (I2C_CR2)
Address offset: 0x04
Reset value: 0x0000
Bit 12 LAST: DMA last transfer
Bit 11 DMAEN: DMA requests enable
Bit 10 ITBUFEN: Buffer interrupt enable
Bit 9 ITEVTEN: Event interrupt enable
Bit 0 PE: Peripheral enable
13
Note: This bit is used in master receiver mode to permit the generation of a NACK on the last
Note: If this bit is reset while a communication is on going, the peripheral is disabled at the
LAST
0: Next DMA EOT is not the last transfer
1: Next DMA EOT is the last transfer
0: DMA requests disabled
1: DMA request enabled when TxE=1 or RxNE =1
0: TxE = 1 or RxNE = 1 does not generate any interrupt.
1:TxE = 1 or RxNE = 1 generates Event Interrupt (whatever the state of DMAEN)
0: Event interrupt disabled
1: Event interrupt enabled
This interrupt is generated when:
0: Peripheral disable
1: Peripheral enable: the corresponding I/Os are selected as alternate functions depending
on SMBus bit.
12
rw
–SB = 1 (Master)
–ADDR = 1 (Master/Slave)
–ADD10= 1 (Master)
–STOPF = 1 (Slave)
–BTF = 1 with no TxE or RxNE event
–TxE event to 1 if ITBUFEN = 1
–RxNE event to 1if ITBUFEN = 1
received data.
end of the current communication, when back to IDLE state.
All bit resets due to PE=0 occur at the end of the communication.
In master mode, this bit must not be reset before the end of the communication.
DMA
EN
11
rw
ITBUF
EN
10
rw
ITEVT
EN
rw
9
Doc ID 13902 Rev 9
ITERR
EN
rw
8
7
Reserved
6
Inter-integrated circuit (I
rw
5
rw
4
rw
FREQ[5:0]
3
rw
2
2
C) interface
rw
1
643/995
rw
0