MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 642

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Inter-integrated circuit (I
642/995
Bit 10 ACK: Acknowledge enable
Bit 9 STOP: Stop generation
Bit 8 START: Start generation
Bit 7 NOSTRETCH: Clock stretching disable (Slave mode)
Bit 6 ENGC: General call enable
Bit 5 ENPEC: PEC enable
Bit 4 ENARP: ARP enable
Bit 3 SMBTYPE: SMBus type
Bit 2 Reserved, forced by hardware to 0.
Bit 1 SMBUS: SMBus mode
Note: When the STOP, START or PEC bit is set, the software must not perform any write
This bit is set and cleared by software and cleared by hardware when PE=0.
0: No acknowledge returned
1: Acknowledge returned after a byte is received (matched address or data)
The bit is set and cleared by software, cleared by hardware when a Stop condition is
detected, set by hardware when a timeout error is detected.
In Master Mode:
0: No Stop generation.
1: Stop generation after the current byte transfer or after the current Start condition is sent.
In Slave mode:
0: No Stop generation.
1: Release the SCL and SDA lines after the current byte transfer.
This bit is set and cleared by software and cleared by hardware when start is sent or PE=0.
In Master Mode:
0: No Start generation
1: Repeated start generation
In Slave mode:
0: No Start generation
1: Start generation when the bus is free
This bit is used to disable clock stretching in slave mode when ADDR or BTF flag is set, until
it is reset by software.
0: Clock stretching enabled
1: Clock stretching disabled
0: General call disabled. Address 00h is NACKed.
1: General call enabled. Address 00h is ACKed.
0: PEC calculation disabled
1: PEC calculation enabled
0: ARP disable
1: ARP enable
SMBus Device default address recognized if SMBTYPE=0
SMBus Host address recognized if SMBTYPE=1
0: SMBus Device
1: SMBus Host
0: I
1: SMBus mode
2
C mode
access to I2C_CR1 before this bit is cleared by hardware. Otherwise there is a risk of
setting a second STOP, START or PEC request.
2
C) interface
Doc ID 13902 Rev 9
RM0008