MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 732

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

USB on-the-go full-speed (OTG_FS)
732/995
Bits 23:22 Reserved
Bits 17:16 Reserved
Bit 25 HCINT: Host channels interrupt
Bit 24 HPRTINT: Host port interrupt
Bit 21 IPXFR: Incomplete periodic transfer
Bit 20 IISOIXFR: Incomplete isochronous IN transfer
Bit 19 OEPINT: OUT endpoint interrupt
Bit 18 IEPINT: IN endpoint interrupt
The core sets this bit to indicate that an interrupt is pending on one of the channels of the core
(in Host mode). The application must read the Host all channels interrupt (OTG_FS_HAINT)
register to determine the exact number of the channel on which the interrupt occurred, and
then read the corresponding Host channel-x interrupt (OTG_FS_HCINTx) register to
determine the exact cause of the interrupt. The application must clear the appropriate status
bit in the OTG_FS_HCINTx register to clear this bit.
Note: Only accessible in Host mode.
The core sets this bit to indicate a change in port status of one of the OTG_FS controller ports
in Host mode. The application must read the Host port control and status (OTG_FS_HPRT)
register to determine the exact event that caused this interrupt. The application must clear the
appropriate status bit in the Host port control and status register to clear this bit.
Note: Only accessible in Host mode.
Note: Only accessible in Host mode.
INCOMPISOOUT: Incomplete isochronous OUT transfer
Note: Only accessible in Device mode.
The core sets this interrupt to indicate that there is at least one isochronous IN endpoint on
which the transfer is not completed in the current frame. This interrupt is asserted along with
the End of periodic frame interrupt (EOPF) bit in this register.
Note: Only accessible in Device mode.
The core sets this bit to indicate that an interrupt is pending on one of the OUT endpoints of
the core (in Device mode). The application must read the Device all endpoints interrupt
(OTG_FS_DAINT) register to determine the exact number of the OUT endpoint on which the
interrupt occurred, and then read the corresponding Device OUT Endpoint-x Interrupt
(OTG_FS_DOEPINTx) register to determine the exact cause of the interrupt. The application
must clear the appropriate status bit in the corresponding OTG_FS_DOEPINTx register to
clear this bit.
Note: Only accessible in Device mode.
The core sets this bit to indicate that an interrupt is pending on one of the IN endpoints of the
core (in Device mode). The application must read the Device All Endpoints Interrupt
(OTG_FS_DAINT) register to determine the exact number of the IN endpoint on which the
interrupt occurred, and then read the corresponding Device IN Endpoint-x interrupt
(OTG_FS_DIEPINTx) register to determine the exact cause of the interrupt. The application
must clear the appropriate status bit in the corresponding OTG_FS_DIEPINTx register to clear
this bit.
Note: Only accessible in Device mode.
In Host mode, the core sets this interrupt bit when there are incomplete periodic transactions
still pending, which are scheduled for the current frame.
In Device mode, the core sets this interrupt to indicate that there is at least one isochronous
OUT endpoint on which the transfer is not completed in the current frame. This interrupt is
asserted along with the End of periodic frame interrupt (EOPF) bit in this register.
Doc ID 13902 Rev 9
RM0008