MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 905

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
27.7
STM32F107xx buffer. The driver must scan all descriptors, from the last recorded position to
the first one owned by the DMA.
An interrupt is generated only once for simultaneous, multiple events. The driver must scan
the ETH_DMASR register for the cause of the interrupt. The interrupt is not generated again
unless a new interrupting event occurs, after the driver has cleared the appropriate bit in the
ETH_DMASR register. For example, the controller generates a Receive interrupt
(ETH_DMASR register[6]) and the driver begins reading the ETH_DMASR register. Next,
receive buffer unavailable (ETH_DMASR register[7]) occurs. The driver clears the Receive
interrupt. Even then, a new interrupt is generated, due to the active or pending Receive
buffer unavailable interrupt.
Figure 318. Interrupt scheme
Ethernet interrupts
The Ethernet controller has two interrupt vectors: one dedicated to normal Ethernet
operations and the other, used only for the Ethernet wakeup event (with wakeup frame or
Magic Packet detection) when it is mapped on EXTI lIne19.
The first Ethernet vector is reserved for interrupts generated by the MAC and the DMA as
listed in the
The second vector is reserved for interrupts generated by the PMT on wakeup events. The
mapping of a wakeup event on EXTI line19 causes the STM32F107xx to exit the low power
mode, and generates an interrupt.
TPSSIE
RWTIE
RWTS
TPSS
TUIE
TUS
TBUIE
TBUS
MAC interrupts
AND
AND
AND
AND
RBUIE
FBEIE
Ethernet (ETH): media access control (MAC) with DMA controller
FBES
ROIE
ETIE
ROS
RBU
ETS
RIE
RS
TIE
TS
AND
AND
AND
AND
and
AND
AND
Doc ID 13902 Rev 9
DMA interrupts
RPSSIE
ERIE
ERS
TJTIE
RPSS
TJTS
AND
AND
AND
sections.
OR
OR
NISE
NIS
AIS
AISE
AND
AND
MMCI
PMTI
TSTI
OR
Interrupt
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