MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 714

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

USB on-the-go full-speed (OTG_FS)
26.11.2
26.12
714/995
data are also stored into the FIFO. The size of the receive FIFO is configured in the receive
FIFO size register (GRXFSIZ).
The single receive FIFO architecture makes it highly efficient for the USB host to fill in the
receive data buffer:
●
●
The application receives the Rx FIFO not-empty interrupt as long as there is at least one
packet available for download. It reads the packet information from the receive status read
and pop register and finally pops the data off the receive FIFO.
Host Tx FIFOs
The host uses one transmit FIFO for all non-periodic (control and bulk) OUT transactions
and one transmit FIFO for all periodic (isochronous and interrupt) OUT transactions. FIFOs
are used as transmit buffers to hold the data (payload of the transmit packet) to be
transmitted over the USB. The size of the periodic (nonperiodic) Tx FIFO is configured in the
host periodic (nonperiodic) transmit FIFO size (HPTXFSIZ/GNPTXFSIZ) register.
The two Tx FIFO implementation derives from the higher priority granted to the periodic type
of traffic over the USB frame. At the beginning of each frame, the built-in host scheduler
processes the periodic request queue first, followed by the nonperiodic request queue.
The two transmit FIFO architecture provides the USB host with separate optimization for
periodic and nonperiodic transmit data buffer management:
●
●
The OTG_FS Core issues the periodic Tx FIFO empty interrupt (PTXFE bit in
OTG_FS_GINTSTS) as long as the periodic Tx-FIFO is half or completely empty, depending
on the value of the periodic Tx-FIFO empty level bit in the AHB configuration register
(PTXFELVL bit in OTG_FS_GAHBCFG). The application can push the transmission data in
advance as long as free space is available in both the periodic Tx FIFO and the periodic
request queue. The host periodic transmit FIFO and queue status register (HPTXSTS) can
be read to know how much space is available in both.
OTG_FS Core issues the non periodic Tx FIFO empty interrupt (NPTXFE bit in
OTG_FS_GINTSTS) as long as the nonperiodic Tx FIFO is half or completely empty
depending on the non periodic Tx FIFO empty level bit in the AHB configuration register
(TXFELVL bit in OTG_FS_GAHBCFG). The application can push the transmission data as
long as free space is available in both the nonperiodic Tx FIFO and nonperiodic request
queue. The host nonperiodic transmit FIFO and queue status register (GNPTXSTS) can be
read to know how much space is available in both.
USB system performance
Best USB and system performance is achieved owing to the large RAM buffers, the highly
configurable FIFO sizes, the quick 32-bit FIFO access through AHB push/pop registers and,
especially, the advanced FIFO control mechanism. Indeed, this mechanism allows the
all IN configured host channels share the same RAM buffer (shared FIFO)
the OTG FS Core can fill in the receive FIFO up to the limit for any sequence of IN
tokens driven by the host software
all host channels configured to support periodic (nonperiodic) transactions in the OUT
direction share the same RAM buffer (shared FIFOs)
the OTG FS Core can fill in the periodic (nonperiodic) transmit FIFO up to the limit for
any sequence of OUT tokens driven by the host software
Doc ID 13902 Rev 9
RM0008