MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 607

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
23.4.3
Clock generator
The I
frequency.
I
For a 16-bit audio, left and right channel, the I
It will be: I
Figure 229. Audio sampling frequency definition
When the master mode is configured, a specific action needs to be taken to properly
program the linear divider in order to communicate with the desired audio frequency.
Figure 230. I
1. Where x could be 2 or 3.
Figure 229
system clock (provided by the HSI, the HSE or the PLL and sourcing the AHB clock). For
connectivity line devices, the I2SxCLK source can be either SYSCLK or the PLL3 VCO
clock in order to have maximum accuracy. This selection is made using the I2S2SRC and
I2S3SRC bits in the RCC_CFGR2 register.
The audio sampling frequency may be 96 kHz, 48 kHz, 44.1 kHz, 32 kHz, 22.05 kHz,
16 kHz, 11.025 kHz or 8 kHz (or any other value within this range). In order to reach the
desired frequency, the linear divider needs to be programmed according to the formulas
below:
2
S bitrate = number of bits per channel × number of channels × sampling audio frequency
I2SxCLK
I
2
2
S bitrate determines the dataflow on the I
S bitrate = 16 × 2 × F
sampling point
2
S bitrate = 32 x 2 x F
presents the communication clock architecture. the I2SxCLK source is the
F
MCKOE
reshaping stage
2
S
: Audio sampling frequency
S clock generator architecture
8-bit
Divider +
ODD
Linear
16-bit or 32-bit Left channel
S
I2SDIV[7:0]
Doc ID 13902 Rev 9
S
if the packet length is 32-bit wide.
32-bits or 64-bits
F
Divider by 4
S
2
16-bit or 32-bit Right channel
S bitrate is calculated as follows:
2
S data line and the I
I2SMOD
Serial peripheral interface (SPI)
Div2
sampling point
2
0
1
S clock signal
MCKOE
CHLEN
0
1
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MCK
CK