MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 896

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MCBSTM32EXL

Manufacturer Part Number
MCBSTM32EXL
Description
BOARD EVALUATION FOR STM32F103ZE
Manufacturer
Keil
Datasheets

Specifications of MCBSTM32EXL

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Ethernet (ETH): media access control (MAC) with DMA controller
896/995
enabled time stamping through CSR, when a valid time stamp value is not available for the
frame (for example, because the receive FIFO was full before the time stamp could be
written to it), the DMA writes all ones to RDES2 and RDES3. Otherwise (that is, if time
stamping is not enabled), RDES2 and RDES3 remain unchanged.
Figure 315. Receive DMA operation
Set descriptor error
No
disabled ?
Flush
intermediate descriptor
Close RDES0 as
Yes
Yes
No
RxDMA suspended
remaining frame
Yes
Flush disabled ?
Frame transfer
for next desc?
Own bit set
complete?
Doc ID 13902 Rev 9
Flush the
Yes
No
No
new frame available
Poll demand /
No
No
Write data to buffer(s)
Fetch next descriptor
Close RDES0 as last
(Re-)Fetch next
Frame transfer
Start RxDMA
Own bit set?
Time stamp
Frame data
available ?
complete?
descriptor
descriptor
present?
(AHB)
error?
(AHB)
error?
(AHB)
error?
(AHB)
error?
Yes
Yes
Yes
No
No
No
No
Yes
Yes
Start
No
No
Wait for frame data
Write time stamp to
RDES2 & RDES3
No
Stop RxDMA
Yes
Yes
Yes
(AHB)
error?
Yes
ai15643
RM0008

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