MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 297

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
13.4.3
ETP
15
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ECE
14
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Bits 13:12 ETPS[1:0]: External trigger prescaler
TIM1&TIM8 slave mode control register (TIMx_SMCR)
Address offset: 0x08
Reset value: 0x0000
Bit 15 ETP: External trigger polarity
Bit 14 ECE: External clock enable
13
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ETPS[1:0]
Note: 1: Setting the ECE bit has the same effect as selecting external clock mode 1 with
This bit selects whether ETR or ETR is used for trigger operations
0: ETR is non-inverted, active at high level or rising edge.
1: ETR is inverted, active at low level or falling edge.
This bit enables External clock mode 2.
0: External clock mode 2 disabled.
1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF
signal.
External trigger signal ETRP frequency must be at most 1/4 of TIMxCLK frequency. A
prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external
clocks.
00: Prescaler OFF.
01: ETRP frequency divided by 2.
10: ETRP frequency divided by 4.
11: ETRP frequency divided by 8.
12
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TRGI connected to ETRF (SMS=111 and TS=111).
2: It is possible to simultaneously use external clock mode 2 with the following slave
modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be
connected to ETRF in this case (TS bits must not be 111).
3: If external clock mode 1 and external clock mode 2 are enabled at the same time,
the external clock input is ETRF.
11
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10
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ETF[3:0]
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9
Doc ID 13902 Rev 9
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8
MSM
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7
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6
Advanced-control timers (TIM1&TIM8)
TS[2:0]
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5
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4
Res.
Res.
3
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2
SMS[2:0]
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1
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