MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 559

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
Note:
A valid edge is defined as the first transition in a bit time from dominant to recessive bus
level provided the controller itself does not send a recessive bit.
If a valid edge is detected in BS1 instead of SYNC_SEG, BS1 is extended by up to SJW so
that the sample point is delayed.
Conversely, if a valid edge is detected in BS2 instead of SYNC_SEG, BS2 is shortened by
up to SJW so that the transmit point is moved earlier.
As a safeguard against programming errors, the configuration of the Bit Timing Register
(CAN_BTR) is only possible while the device is in Standby mode.
For a detailed description of the CAN bit timing and resynchronization mechanism, please
refer to the ISO 11898 standard.
Figure 204. Bit timing
BaudRate
BRP[9:0], TS1[3:0] and TS2[2:0] are defined in the CAN_BTR Register.
NominalBitTime
with:
SYNC_SEG
t
t
t
t
BS1
BS2
q
PCLK
1 x t
= (BRP[9:0] + 1) x t
where t
q
= t
= t
= time period of the APB clock,
q
q
=
x (TS1[3:0] + 1),
x (TS2[2:0] + 1),
----------------------------------------------
NominalBitTime
q
refers to the Time quantum
=
1
BIT SEGMENT 1 (BS1)
1

t
q
PCLK
+
Doc ID 13902 Rev 9
t
BS1
t
BS1
NOMINAL BIT TIME
+
t
BS2
SAMPLE POINT
Controller area network (bxCAN)
BIT SEGMENT 2 (BS2)
t
BS2
TRANSMIT POINT
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