MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 972

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Debug support (DBG)
29.16.2
29.16.3
972/995
DBG_I2C1
_SMBUS_
TIMEOUT
31
15
rw
CAN1_
DBG_
STOP
30
14
rw
For this, the debugger host must first set some debug configuration registers to change the
low-power mode behavior:
●
●
Debug support for timers, watchdog, bxCAN and I
During a breakpoint, it is necessary to choose how the counter of timers and watchdog
should behave:
●
●
For the bxCAN, the user can choose to block the update of the receive register during a
breakpoint.
For the I
Debug MCU configuration register
This register allows the configuration of the MCU under DEBUG. This concerns:
●
●
●
●
This DBGMCU_CR is mapped on the External PPB bus at address 0xE0042004
It is asynchronously reset by the PORESET (and not the system reset). It can be written by
the debugger under system reset.
If the debugger host does not support these features, it is still possible for the user software
to write to these registers.
DBGMCU_CR
Address: 0xE004 2004
Only 32-bit access supported
POR Reset: 0x0000 0000 (not reset by system reset)
TIM4_
DBG_
STOP
29
13
rw
In Sleep mode, DBG_SLEEP bit of DBGMCU_CR register must be previously set by
the debugger. This will feed HCLK with the same clock that is provided to FCLK
(system clock previously configured by the software).
In STOP mode, the bit DBG_STOP must be previously set by the debugger. This will
enable the internal RC oscillator clock to feed FCLK and HCLK in STOP mode.
they can continue to count inside a breakpoint. This is usually required when a PWM is
controlling a motor, for example.
they can stop to count inside a breakpoint. This is required for watchdog purposes.
Low-power mode support
Timer and watchdog counters support
bxCAN communication support
Trace pin assignment
2
DBG_
TIM3_
STOP
C, the user can choose to block the SMBUS timeout during a breakpoint.
28
12
rw
TIM2_
DBG_
STOP
Reserved
27
11
rw
TIM1_
DBG_
STOP
26
10
rw
WWDG_
DBG_
STOP
25
rw
9
Doc ID 13902 Rev 9
DBG_
IWDG
STOP
24
rw
8
23
rw
TRACE_
7
MODE
[1:0]
22
rw
6
TRACE_
AN2_ST
DGB_C
IOEN
OP
21
rw
rw
5
TIM7_
DBG_
STOP
20
rw
4
Reserved
TIM6_
DBG_
STOP
2
19
rw
C
3
STAND
TIM5_
DBG_
STOP
DBG_
BY
18
rw
rw
2
TIM8_
DBG_
STOP
DBG_
STOP
17
rw
rw
1
RM0008
DBG_I2C2
_SMBUS_
TIMEOUT
SLEEP
DBG_
16
rw
rw
0