MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 136

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Connectivity line devices: reset and clock control (RCC)
7.3.13
Table 16.
136/995
Offset
0x00C
0x000
0x004
0x008
0x010
RCC_APB2RSTR
RCC_APB1RSTR Reser
RCC_CFGR
Reset value
Reset value
Reset value
Reset value
Reset value
Register
RCC_CIR
RCC_CR
Bits 3:0 PREDIV1[3:0]: PREDIV1 division factor
RCC register map
The following table gives the RCC register map and the reset values.
RCC register map and reset values
Note: Bit(0) is the same as bit(17) in the RCC_CFGR register, so modifying bit(17) in the
Reser
Set and cleared by software to select PREDIV1 division factor. These bits can be written only
when PLL is disabled.
0000: PREDIV1 input clock not divided
0001: PREDIV1 input clock divided by 2
0010: PREDIV1 input clock divided by 3
0011: PREDIV1 input clock divided by 4
0100: PREDIV1 input clock divided by 5
0101: PREDIV1 input clock divided by 6
0110: PREDIV1 input clock divided by 7
0111: PREDIV1 input clock divided by 8
1000: PREDIV1 input clock divided by 9
1001: PREDIV1 input clock divided by 10
1010: PREDIV1 input clock divided by 11
1011: PREDIV1 input clock divided by 12
1100: PREDIV1 input clock divided by 13
1101: PREDIV1 input clock divided by 14
1110: PREDIV1 input clock divided by 15
1111: PREDIV1 input clock divided by 16
ved
ved
Reserved
RCC_CFGR register changes Bit(0) accordingly.
0
0
Reserved
0
0
0
0
0
MCO [3:0]
0
0
0
0
0
0
Reserved
0
0
0
Reserved
Doc ID 13902 Rev 9
0
0
0
PLLMUL [3:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
x
ADC
0
0
PRE
[1:0]
x
0
0
0
0
HSICAL[7:0]
x
0
0
PPRE2
[2:0]
0
0
0
x
0
0
0
0
x
x
0
0
0
PPRE1
[2:0]
Reserved
x
0
0
0
x
0
0
1
0
0
HPRE[3:0]
HSITRIM[4:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SWS
0
0
0
0
0
[1:0]
RM0008
0
0
0
0
1
0
0
0
[1:0]
SW
1
0
0
0
0