MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 877

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
Programming steps for system time update in the Coarse correction method
To synchronize or update the system time in one process (coarse correction method),
perform the following steps:
1.
2.
3.
Programming steps for system time update in the Fine correction method
To synchronize or update the system time to reduce system-time jitter (fine correction
method), perform the following steps:
1.
2.
3.
4.
5.
6.
7.
PTP trigger internal connection with TIM2
The MAC provides a trigger interrupt when the system time becomes greater than the target
time. Using an interrupt introduces a known latency plus an uncertainty in the command
execution time.
In order to avoid this uncertainty, a PTP trigger output signal is set high when the system
time is greater than the target time. It is internally connected to the TIM2 input trigger. With
this signal, the input capture feature, the output compare feature and the waveforms of the
timer can be used, triggered by the synchronized PTP system time. No uncertainty is
introduced since the clock of the timer (PCLK1: TIM2 APB1 clock) and PTP reference clock
(HCLK) are synchronous.
This PTP trigger signal is connected to the TIM2 ITR1 input selectable by software. The
connection is enabled through bit 29 in the AFIO_MAPR register.
connection.
Figure 308. PTP trigger output to TIM2 ITR1 connection
Write the offset (positive or negative) in the Time stamp update high and low registers.
Set bit 3 (TSSTU) in the Time stamp control register.
The value in the Time stamp update registers is added to or subtracted from the system
time when the TSSTU bit is cleared.
With the help of the algorithm explained in
calculate the rate by which you want to speed up or slow down the system time
increments.
Update the time stamp.
Wait the time you want the new value of the Addend register to be active. You can do
this by activating the Time stamp trigger interrupt after the system time reaches the
target value.
Program the required target time in the Target time high and low registers. Unmask the
Time stamp interrupt by clearing bit 9 in the ETH_MACIMR register.
Set Time stamp control register bit 4 (TSARU).
When this trigger causes an interrupt, read the ETH_MACSR register.
Reprogram the Time stamp addend register with the old value and set ETH_TPTSCR
bit 5 again.
Ethernet (ETH): media access control (MAC) with DMA controller
Ethernet MAC
Doc ID 13902 Rev 9
PTP trigger
Section : System Time correction
ITR1
TIM2
Figure 308
shows the
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methods,
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