MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 982

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision history
982/995
Table 215. Document revision history (continued)
19-Oct-2007
continued
Date
continued
Revision
1
Figure 113: Counter timing diagram, internal clock divided by 1,
TIMx_ARR=0x6
modified. CKD definition modified in
(TIMx_CR1).
Bit 8 and Bit 9 added to
(BKP_RTCCR).
it 15 and Bit 16 added to
debug mode on page 640
Stop and Standby modified in
Table 10: Sleep-on-exit
HSITRIM[4:0] bit description modified in
(RCC_CR). Note modified in MCO description in
configuration register
map and reset values on page
Bits 15:0 description modified in
(GPIOx_BRR)
Figure
Section 2.3.3: Embedded Flash memory on page 44
REV_ID bit description added to
Reset value modified in
HSITRIM[4:0] description modified.
Section 8.1.1 on page 140
GPIO registers on page
Table 11: Stop
Clock control register (RCC_CR)
Note added in ASOS and ASOE bit descriptions in
Section 29.16.2: Debug support for timers, watchdog, bxCAN and I
modified.
Section 21.5.3: Buffer descriptor table
Center-aligned mode (up/down counting) on page 262
mode (up/down counting) on page 328
Figure 84: Center-aligned PWM waveforms (ARR=8) on page 277
Figure 130: Center-aligned PWM waveforms (ARR=8) on page 341
modified.
RSTCAL description modified in
(ADC_CR2).
Note changed below
clock)Min/max IWDG timeout period at 32 kHz
Figure 8: Clock
ADC conversion time modified in
Auto-injection on page 204
Note added in
interleaved. Note added to
GPIO ports
changed from 32 to 40 kHz.
input clock)Min/max IWDG timeout period at 32 kHz (LSI)
byte addresses corrected in
module organization (medium-density
organization modified in
External event that trigger ADC conversion is EXTI line instead of external
interrupt (see
Appendix A: Important notes on page 500
13,
Doc ID 13902 Rev 9
Table 214: DBG register map and reset values
Figure
PD0/PD1. Small text changes. Internal LSI RC frequency
Section 11: Analog-to-digital converter
Section 11.9.9: Combined injected simultaneous +
(x=A..G).
mode.
tree.
and
15,
Figure 128: Output compare mode, toggle on OC1.
Table 81: Watchdog timeout period (with 40 kHz input
(RCC_CFGR). RCC_CR row modified in
Figure
modified.
Section 5.4.2: RTC clock calibration register
Clock control register (RCC_CR) on page 83
148. Wakeup latency description modified in
Section 2.3.3: Embedded Flash
Embedded boot loader on page 49
DBGMCU_CR on page
added.
Section 8.3.2: Using OSC_IN/OSC_OUT pins as
modified. Bit definitions modified in
updated.
Table 81: Watchdog timeout period (with 40 kHz
Figure 2: Memory map
16,
Table 8: Low-power mode
102.
Figure 17
Section 8.2.6: Port bit reset register
Section 11.12.3: ADC control register 2
DBGMCU_IDCODE on page
Changes
reset value modified.
Section 11.2: ADC main
Debug mode on page 62
Section 14.4.1: TIMx control register 1
clarified.
devices). Information block
updated.
Section 6.3.1: Clock control register
added.
and
Figure 18
(LSI). Note added below
972.
Section 6.3.2: Clock
5.4.2 on page
and
modified.
(ADC)).
Section 24.5: I
and
Table 3: Flash
summary.
updated.
memory.
modified.
features.
updated. Option
modified.
Center-aligned
added.
RCC register
959.
Section 8.2:
68.
and
2
RM0008
C
2
and
C