MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 532

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Universal serial bus full-speed device interface (USB)
21.5.2
532/995
CTR_
rc_w0
RX
15
rw
15
DTOG
_RX
14
rw
14
t
Bits 15:3 BTABLE[15:3]: Buffer table
Bits 6:0 ADD[6:0]: Device address
Bits 2:0 Reserved, forced by hardware to 0.
Buffer table address (USB_BTABLE)
Address offset: 0x50
Reset value: 0x0000
Endpoint-specific registers
The number of these registers varies according to the number of endpoints that the USB
peripheral is designed to handle. The USB peripheral supports up to 8 bidirectional
endpoints. Each USB device must support a control endpoint whose address (EA bits) must
be set to 0. The USB peripheral behaves in an undefined way if multiple endpoints are
enabled having the same endpoint number value. For each endpoint, an USB_EPnR
register is available to store the endpoint specific information.
USB endpoint n register (USB_EPnR), n=[0..7]
Address offset: 0x00 to 0x1C
Reset value: 0x0000
They are also reset when an USB reset is received from the USB bus or forced through bit
FRES in the CTLR register, except the CTR_RX and CTR_TX bits, which are kept
unchanged to avoid missing a correct packet notification immediately followed by an USB
reset event. Each endpoint has its USB_EPnR register where n is the endpoint identifier.
STAT_RX[1:0]
13
rw
13
t
These bits contain the USB function address assigned by the host PC during the
enumeration process. Both this field and the Endpoint Address (EA) field in the associated
USB_EPnR register must match with the information contained in a USB token in order to
handle a transaction to the required endpoint.
These bits contain the start address of the buffer allocation table inside the dedicated packet
memory. This table describes each endpoint buffer location and size and it must be aligned
to an 8 byte boundary (the 3 least significant bits are always ‘0’). At the beginning of every
transaction addressed to this device, the USP peripheral reads the element of this table
related to the addressed endpoint, to get its buffer start location and the buffer size (Refer to
Structure and usage of packet buffers on page
12
rw
12
t
SETUP
11
rw
11
r
10
rw
10
rw
TYPE[1:0]
BTABLE[15:3]
EP
rw
9
rw
9
Doc ID 13902 Rev 9
KIND
rw
EP_
8
rw
8
CTR_
rc_w0
rw
7
TX
7
DTOG_
rw
6
TX
6
t
516).
rw
5
STAT_TX[1:0]
5
t
rw
4
4
t
rw
3
rw
3
2
rw
2
EA[3:0]
Reserved
Res.
1
rw
1
RM0008
0
rw
0