MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 4
MCBSTM32EXL
Manufacturer Part Number
MCBSTM32EXL
Description
BOARD EVALUATION FOR STM32F103ZE
Manufacturer
Keil
Specifications of MCBSTM32EXL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 4 of 995
- Download datasheet (9Mb)
Contents
7
4/995
6.3
Connectivity line devices: reset and clock control (RCC) . . . . . . . . . 104
7.1
7.2
7.3
6.2.7
6.2.8
6.2.9
6.2.10
RCC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.3.7
6.3.8
6.3.9
6.3.10
6.3.11
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
7.1.1
7.1.2
7.1.3
Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
7.2.8
7.2.9
7.2.10
RCC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
7.3.1
7.3.2
7.3.3
Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
RTC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Watchdog clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Clock control register (RCC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Clock configuration register (RCC_CFGR) . . . . . . . . . . . . . . . . . . . . . . 84
Clock interrupt register (RCC_CIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
APB2 peripheral reset register (RCC_APB2RSTR) . . . . . . . . . . . . . . . 89
APB1 peripheral reset register (RCC_APB1RSTR) . . . . . . . . . . . . . . . 91
AHB peripheral clock enable register (RCC_AHBENR) . . . . . . . . . . . . 93
APB2 peripheral clock enable register (RCC_APB2ENR) . . . . . . . . . . . 95
APB1 peripheral clock enable register (RCC_APB1ENR) . . . . . . . . . . . 97
Backup domain control register (RCC_BDCR) . . . . . . . . . . . . . . . . . . . 99
Control/status register (RCC_CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
RCC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Power reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Backup domain reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
HSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
HSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
LSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
LSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
System clock (SYSCLK) selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
RTC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Watchdog clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Clock control register (RCC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Clock configuration register (RCC_CFGR) . . . . . . . . . . . . . . . . . . . . . 115
Clock interrupt register (RCC_CIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Doc ID 13902 Rev 9
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