MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 885

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
Figure 312. TxDMA operation in OSF mode
Transmit frame processing
The transmit DMA expects that the data buffers contain complete Ethernet frames,
excluding preamble, pad bytes, and FCS fields. The DA, SA, and Type/Len fields contain
valid data. If the transmit descriptor indicates that the MAC core must disable CRC or pad
insertion, the buffer must have complete Ethernet frames (excluding preamble), including
the CRC bytes. Frames can be data-chained and span over several buffers. Frames have to
be delimited by the first descriptor (TDES0[28]) and the last descriptor (TDES0[29]). As the
transmission starts, TDES0[28] has to be set in the first descriptor. When this occurs, the
frame data are transferred from the memory buffer to the Transmit FIFO. Concurrently, if the
last descriptor (TDES0[29]) of the current frame is cleared, the transmit process attempts to
acquire the next descriptor. The transmit process expects TDES0[28] to be cleared in this
descriptor. If TDES0[29] is cleared, it indicates an intermediary buffer. If TDES0[29] is set, it
No
No
prev. frame’s TDES0
Write status word to
Write time stamp to
TxDMA suspended
for previous frame
TDES2 & TDES3
status available
Previous frame
Time stamp
present?
demand
(AHB)
error?
(AHB)
error?
Yes
Poll
No
Yes
Ethernet (ETH): media access control (MAC) with DMA controller
Yes
Doc ID 13902 Rev 9
Close intermediate
descriptor
No
No
No
prev. frame’s TDES0
Write status word to
Transfer data from
(Re-)fetch next
Start TxDMA
Time stamp
Frame xfer
complete?
descriptor
present?
buffer(s)
bit set?
(AHB)
error?
(AHB)
error?
(AHB)
error?
Own
Yes
No
No
Yes
No
Yes
Yes
Yes
Yes
Start
No
Write time stamp to
for previous frame
TDES2 & TDES3
frame’s Tx status
Wait for previous
Stop TxDMA
Second
frame?
(AHB)
error?
Yes
No
Yes
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