MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 659

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
Figure 240. Configurable stop bits
Procedure:
1.
2.
3.
4.
5.
6.
7.
8.
Single byte communication
Clearing the TXE bit is always performed by a write to the data register.
The TXE bit is set by hardware and it indicates:
●
●
●
This flag generates an interrupt if the TXEIE bit is set.
Enable the USART by writing the UE bit in USART_CR1 register to 1.
Program the M bit in USART_CR1 to define the word length.
Program the number of stop bits in USART_CR2.
Select DMA enable (DMAT) in USART_CR3 if Multi buffer Communication is to take
place. Configure the DMA register as explained in multibuffer communication.
Select the desired baud rate using the USART_BRR register.
Set the TE bit in USART_CR1 to send an idle frame as first transmission.
Write the data to send in the USART_DR register (this clears the TXE bit). Repeat this
for each data to be transmitted in case of single buffer.
After writing the last data into the USART_DR register, wait until TC=1. This indicates
that the transmission of the last frame is complete. This is required for instance when
the USART is disabled or enters the Halt mode to avoid corrupting the last
transmission.
The data has been moved from TDR to the shift register and the data transmission has
started.
The TDR register is empty.
The next data can be written in the USART_DR register without overwriting the
previous data.
CLOCK
a) 1 Stop Bit
b) 1 1/2 stop Bits
c) 2 Stop Bits
d) 1/2 Stop Bit
8-bit Word length (M bit is reset)
Start
Start
Start
Start
Bit
Bit
Bit
Bit
Universal synchronous asynchronous receiver transmitter (USART)
Bit0
Bit0
Bit0
Bit0
Bit1
Bit1
Bit1
Bit1
Data Frame
Data Frame
Data Frame
Data Frame
Doc ID 13902 Rev 9
Bit2
Bit2
Bit2
Bit2
Bit3
Bit3
Bit3
Bit3
Bit4
Bit4
Bit4
Bit4
Bit5
Bit5
Bit5
Bit5
Bit6
Bit6
Bit6
Bit6
Possible
Possible
Possible
Possible
Parity
Parity
Parity
Parity
Bit7
Bit
Bit
Bit
Bit7
Bit
Bit7
****
Bit7
** LBCL bit controls last data clock pulse
**
1 1/2 stop bits
1/2 stop bit
Stop
2 Stop
Bit
Bits
Next
Start
Bit
Next
Start
Bit
Next
Start
Bit
Next Data Frame
Next Data Frame
Next Data Frame
Next Data Frame
Next
Start
Bit
659/995