MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 194

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MCBSTM32EXL

Manufacturer Part Number
MCBSTM32EXL
Description
BOARD EVALUATION FOR STM32F103ZE
Manufacturer
Keil
Datasheets

Specifications of MCBSTM32EXL

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
DMA controller (DMA)
10.4.4
194/995
31
15
rw
30
14
rw
Bits 31:16
Bits 15:0 NDT[15:0]: Number of data to transfer
DMA channel x number of data register (DMA_CNDTRx) (x = 1 ..7)
Address offset: 0x0C + 20d × Channel number
Reset value: 0x0000 0000
Bit 5 CIRC: Circular mode
Bit 4 DIR: Data transfer direction
Bit 3 TEIE: Transfer error interrupt enable
Bit 2 HTIE: Half transfer interrupt enable
Bit 1 TCIE: Transfer complete interrupt enable
Bit 0 EN: Channel enable
29
13
rw
This bit is set and cleared by software.
0: Circular mode disabled
1: Circular mode enabled
This bit is set and cleared by software.
0: Read from peripheral
1: Read from memory
This bit is set and cleared by software.
0: TE interrupt disabled
1: TE interrupt enabled
This bit is set and cleared by software.
0: HT interrupt disabled
1: HT interrupt enabled
This bit is set and cleared by software.
0: TC interrupt disabled
1: TC interrupt enabled
This bit is set and cleared by software.
0: Channel disabled
1: Channel enabled
28
12
rw
Reserved, always read as 0.
Number of data to be transferred (0 up to 65535). This register can only be written when the
channel is disabled. Once the channel is enabled, this register is read-only, indicating the
remaining bytes to be transmitted. This register decrements after each DMA transfer.
Once the transfer is completed, this register can either stay at zero or be reloaded
automatically by the value previously programmed if the channel is configured in auto-reload
mode.
If this register is zero, no transaction can be served whether the channel is enabled or not.
27
11
rw
26
10
rw
25
rw
9
Doc ID 13902 Rev 9
24
rw
8
Reserved
NDT
23
rw
7
22
rw
6
21
rw
5
20
rw
4
19
rw
3
18
rw
2
17
rw
1
RM0008
16
rw
0

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