MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 913

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
Bits 31:16 PT: Pause time
Bits 15:8 Reserved
Bits 5:4 PLT: Pause low threshold
Bit 7 ZQPD: Zero-quanta pause disable
Bit 6 Reserved
Bit 3 UPFD: Unicast pause frame detect
Bit 2 RFCE: Receive flow control enable
Bit 1 TFCE: Transmit flow control enable
This field holds the value to be used in the Pause Time field in the transmit control frame. If the
Pause Time bits is configured to be double-synchronized to the MII clock domain, then
consecutive write operations to this register should be performed only after at least 4 clock
cycles in the destination clock domain.
When set, this bit disables the automatic generation of Zero-quanta pause control frames on
the deassertion of the flow-control signal from the FIFO layer.
When this bit is reset, normal operation with automatic Zero-quanta pause control frame
generation is enabled.
This field configures the threshold of the Pause timer at which the Pause frame is
automatically retransmitted. The threshold values should always be less than the Pause Time
configured in bits[31:16]. For example, if PT = 100H (256 slot-times), and PLT = 01, then a
second PAUSE frame is automatically transmitted if initiated at 228 (256 – 28) slot-times after
the first PAUSE frame is transmitted.
Slot time is defined as time taken to transmit 512 bits (64 bytes) on the MII interface.
When this bit is set, the MAC detects the Pause frames with the station’s unicast address
specified in the ETH_MACA0HR and ETH_MACA0LR registers, in addition to detecting Pause
frames with the unique multicast address.
When this bit is reset, the MAC detects only a Pause frame with the unique multicast address
specified in the 802.3x standard.
When this bit is set, the MAC decodes the received Pause frame and disables its transmitter
for a specified (Pause Time) time.
When this bit is reset, the decode function of the Pause frame is disabled.
In Full-duplex mode, when this bit is set, the MAC enables the flow control operation to
transmit Pause frames. When this bit is reset, the flow control operation in the MAC is
disabled, and the MAC does not transmit any Pause frames.
In Half-duplex mode, when this bit is set, the MAC enables the back-pressure operation. When
this bit is reset, the back pressure feature is disabled.
Selection
00
01
10
11
Ethernet (ETH): media access control (MAC) with DMA controller
Threshold
Pause time minus 4 slot times
Pause time minus 28 slot times
Pause time minus 144 slot times
Pause time minus 256 slot times
Doc ID 13902 Rev 9
913/995