MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 407

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MCBSTM32EXL

Manufacturer Part Number
MCBSTM32EXL
Description
BOARD EVALUATION FOR STM32F103ZE
Manufacturer
Keil
Datasheets

Specifications of MCBSTM32EXL

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
RM0008
18.6
18.6.1
18.6.2
31
15
31
15
30
14
30
14
Bit 31:10 Reserved
Bits 31:8 Reserved
Bits 6:0 T[6:0]: 7-bit counter (MSB to LSB)
WWDG registers
Refer to
Control register (WWDG_CR)
Address offset: 0x00
Reset value: 0x7F
Configuration register (WWDG_CFR)
Address offset: 0x04
Reset value: 0x7F
Bit 7 WDGA: Activation bit
Bit 9 EWI: Early wakeup interrupt
29
13
29
13
Reserved
28
12
This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
These bits contain the value of the watchdog counter. It is decremented every (4096 x
2
cleared).
28
12
When set, an interrupt occurs whenever the counter reaches the value 40h. This interrupt is
only cleared by hardware after a reset.
Section 1.1 on page 37
Reserved
WDGTB
27
11
27
11
) PCLK1 cycles. A reset is produced when it rolls over from 40h to 3Fh (T6 becomes
26
10
26
10
EWI
25
25
rs
9
9
Doc ID 13902 Rev 9
for a list of abbreviations used in register descriptions.
WDG
TB1
24
24
rw
8
8
Reserved
Reserved
WDGA
WDG
TB0
23
23
rw
rs
7
7
W6
22
T6
22
rw
rw
6
6
W5
21
T5
rw
21
rw
5
5
W4
T4
20
rw
20
rw
4
4
Window watchdog (WWDG)
W3
T3
19
rw
19
rw
3
3
W2
18
T2
18
rw
rw
2
2
W1
17
T1
17
rw
rw
1
1
407/995
W0
T0
16
rw
16
rw
0
0

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