MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 609

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
Table 167. Audio-frequency precision using standard 14.7456 MHz and PLL3 (connectivity line
23.4.4
16-bit 32-bit 16-bit 32-bit 16-bit 32-bit 16-bit 32-bit
11
11
12
11
PREDIV2
3
6
2
4
2
2
6
2
2
4
4
6
11
11
12
11
3
6
2
4
2
2
6
2
2
4
4
6
devices only)
I
The I
the CK pin as well as the Word Select signal WS. Master clock (MCK) may be output or not,
thanks to the MCKOE bit in the SPI_I2SPR register.
Procedure
1.
2.
3.
2
S master mode
10
20
20
10
10
20
10
20
10
20
10
10
13
20
20
20
PLL3
Select the I2SDIV[7:0] bits in the SPI_I2SPR register to define the serial clock baud
rate to reach the proper audio sample frequency. The ODD bit in the SPI_I2SPR
register also has to be defined.
Select the CKPOL bit to define the steady level for the communication clock. Set the
MCKOE bit in the SPI_I2SPR register if the master clock MCK needs to be provided to
the external DAC/ADC audio component (the I2SDIV and ODD values should be
computed depending on the state of the MCK output, for more details refer to
Section 23.4.3: Clock
Set the I2SMOD bit in SPI_I2SCFGR to activate the I
I
DATLEN[1:0] bits and the number of bits per channel by configuring the CHLEN bit.
Select also the I
I2SCFG[1:0] bits in the SPI_I2SCFGR register.
2
2
S can be configured in master mode. This means that the serial clock is generated on
S standard through the I2SSTD[1:0] and PCMSYNC bits, the data length through the
10
20
20
10
10
20
10
20
10
20
10
10
13
20
20
20
144
209
16
32
19
72
19
96
18
24
3
4
6
9
8
9
I2SDIV
2
S master mode and direction (Transmitter or Receiver) through the
104
16
36
72
48
18
24
8
9
9
3
4
6
9
8
9
generator).
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
I2SODD
Doc ID 13902 Rev 9
0
0
1
0
1
0
1
0
0
0
1
0
1
0
1
0
No
No
No
No
No
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
MCLK
96000
48000
44100
32000
22050
16000
11025
8000
96000
48000
44100
32000
22050
16000
11025
8000
F
Target
S
(Hz)
96000
48000
44095.69 44095.69 0.0098% 0.0098%
32000
22047.84 22047.84 0.0098% 0.0098%
16000
11023.92 11023.92 0.0098% 0.0098%
8000
96000
48000
44307.69 44307.69 0.4710
32000
22023.52 22023.52 0.1200% 0.1200%
16000
11023.92 11023.92 0.0098% 0.0098%
8000
16-bit
Serial peripheral interface (SPI)
2
Real F
S functionalities and choose the
S
96000
48000
32000
16000
8000
96000
48000
32000
16000
8000
(kHz)
32-bit
0%
0%
0%
0%
0%
0%
0%
0%
0%
0%
16-bit
Error
0%
0%
0%
0%
0%
0%
0%
0.4710%
0%
0%
0%
609/995
32-bit