MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 299

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
13.4.4
Res.
Res.
15
TDE
14
rw
Bits 2:0 SMS: Slave mode selection
Table 72.
1. When a timer is not present in the product, the corresponding trigger ITRx is not available.
TIM1&TIM8 DMA/interrupt enable register (TIMx_DIER)
Address offset: 0x0C
Reset value: 0x0000
Bit 15 Reserved, always read as 0.
Bit 14 TDE: Trigger DMA request enable
Bit 13 COMDE: COM DMA request enable
COMD
13
rw
Slave TIM
E
TIM1
TIM8
Note: The gated mode must not be used if TI1F_ED is selected as the trigger input
CC4D
When external signals are selected the active edge of the trigger signal (TRGI) is linked to
the polarity selected on the external input (see Input Control register and Control Register
description.
000: Slave mode disabled - if CEN = ‘1’ then the prescaler is clocked directly by the internal
clock.
001: Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1
level.
010: Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2
level.
011: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges
depending on the level of the other input.
100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter
and generates an update of the registers.
101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The
counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of
the counter are controlled.
110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not
reset). Only the start of the counter is controlled.
111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
0: Trigger DMA request disabled.
1: Trigger DMA request enabled.
0: COM DMA request disabled.
1: COM DMA request enabled.
12
rw
E
(TS=’100’). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the
gated mode checks the level of the trigger signal.
TIMx Internal trigger connection
CC3D
11
rw
E
ITR0 (TS = 000)
CC2D
10
rw
E
TIM5
TIM1
CC1D
rw
9
E
Doc ID 13902 Rev 9
UDE
rw
8
ITR1 (TS = 001)
BIE
rw
TIM2
TIM2
7
(1)
TIE
rw
6
Advanced-control timers (TIM1&TIM8)
COMI
rw
5
E
ITR2 (TS = 010)
CC4IE
TIM3
TIM4
rw
4
CC3IE
rw
3
CC2IE
rw
ITR3 (TS = 011)
2
CC1IE
TIM4
TIM5
rw
1
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UIE
rw
0