MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 175

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
9.2.1
9.2.2
9.2.3
Main features
The EXTI controller main features are the following:
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Block diagram
The block diagram is shown in
Figure 20. External interrupt/event controller block diagram
Wakeup event management
The STM32F10xxx is able to handle external or internal events in order to wake up the core
(WFE). The wakeup event can be generated either by:
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Independent trigger and mask on each interrupt/event line
Dedicated status bit for each interrupt line
Generation of up to 20 software event/interrupt requests
Detection of external signal with pulse width lower than APB2 clock period. Refer to the
electrical characteristics section of the datasheet for details on this parameter.
enabling an interrupt in the peripheral control register but not in the NVIC, and enabling
the SEVONPEND bit in the Cortex-M3 System Control register. When the MCU
resumes from WFE, the peripheral interrupt pending bit and the peripheral NVIC IRQ
channel pending bit (in the NVIC interrupt clear pending register) have to be cleared.
or configuring an external or internal EXTI line in event mode. When the CPU resumes
from WFE, it is not necessary to clear the peripheral interrupt pending bit or the NVIC
IRQ channel pending bit as the pending bit corresponding to the event line is not set.
20
To NVIC Interrupt
Controller
PCLK2
20
generator
Pulse
20
Interrupt
20
register
mask
20
Doc ID 13902 Rev 9
Figure
20
register
Event
mask
Pending
request
register
20.
20
AMBA APB bus
Peripheral interface
Software
interrupt
register
20
event
20
20
selection
register
trigger
Rising
20
Edge detect
20
circuit
selection
register
Falling
trigger
Interrupts and events
20
20
Input
Line
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