MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 333

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
The delay between the rising edge on TI2 and the actual clock of the counter is due to the
resynchronization circuit on TI2 input.
Figure 121. Control circuit in external clock mode 1
External clock source mode 2
This mode is selected by writing ECE=1 in the TIMx_SMCR register.
The counter can count at each rising or falling edge on the external trigger input ETR.
The
Figure 122. External trigger input block
For example, to configure the upcounter to count each 2 rising edges on ETR, use the
following procedure:
1.
2.
3.
4.
5.
The counter counts once each 2 ETR rising edges.
The delay between the rising edge on ETR and the actual clock of the counter is due to the
resynchronization circuit on the ETRP signal.
ETR pin
Figure 122
As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register.
Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register
Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR
register
Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register.
Enable the counter by writing CEN=1 in the TIMx_CR1 register.
Counter clock = CK_CNT = CK_PSC
ETR
TIMx_SMCR
gives an overview of the external trigger input block.
ETP
0
1
Counter register
/1, /2, /4, /8
ETPS[1:0]
TIMx_SMCR
CNT_EN
Doc ID 13902 Rev 9
divider
TIF
TI2
CK_INT
ETRP
34
Write TIF=0
downcounter
ETF[3:0]
TIMx_SMCR
filter
35
General-purpose timer (TIMx)
or
CK_INT
(internal clock)
TI2F
TI1F
TRGI
ETRF
or
or
ECE
encoder
mode
external clock
mode 1
external clock
mode 2
internal clock
mode
36
TIMx_SMCR
SMS[2:0]
333/995
CK_PSC