MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 384

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Basic timers (TIM6&TIM7)
15.4.4
15.4.5
15.4.6
384/995
15
15
15
rw
Bits 15:0
14
14
14
rw
Bits 15:1 Reserved, always read as 0.
Bits 15:1 Reserved, always read as 0.
TIM6&TIM7 status register (TIMx_SR)
Address offset: 0x10
Reset value: 0x0000
TIM6&TIM7 event generation register (TIMx_EGR)
Address offset: 0x14
Reset value: 0x0000
TIM6&TIM7 counter (TIMx_CNT)
Address offset: 0x24
Reset value: 0x0000
Bit 0 UG: Update generation
Bit 0 UIF: Update interrupt flag
13
13
13
rw
CNT[15:0]: Counter value
This bit can be set by software, it is automatically cleared by hardware.
0: No action.
1: Re-initializes the timer counter and generates an update of the registers. Note that the
prescaler counter is cleared too (but the prescaler ratio is not affected).
This bit is set by hardware on an update event. It is cleared by software.
0: No update occurred.
1: Update interrupt pending. This bit is set by hardware when the registers are updated:
12
12
12
rw
–At overflow or underflow regarding the repetition counter value and if UDIS = 0 in the
–When CNT is reinitialized by software using the UG bit in the TIMx_EGR register, if
TIMx_CR1 register.
URS = 0 and UDIS = 0 in the TIMx_CR1 register.
11
11
11
rw
10
10
10
rw
rw
9
9
9
Doc ID 13902 Rev 9
Reserved
Reserved
rw
8
8
8
CNT[15:0]
rw
7
7
7
rw
6
6
6
rw
5
5
5
rw
4
4
4
rw
3
3
3
rw
2
2
2
rw
1
1
1
RM0008
rc_w0
UIF
UG
rw
w
0
0
0