MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 498

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Secure digital input/output interface (SDIO)
Note:
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Bits 31:0 CMDARG: Command argument
Bits 7:0 CLKDIV: Clock divide factor
While the SD/SDIO card or MultiMediaCard is in identification mode, the SDIO_CK
frequency must be less than 400 kHz.
The clock frequency can be changed to the maximum card bus frequency when relative
card addresses are assigned to all cards.
After a data write, data cannot be written to this register for seven HCLK clock periods.
SDIO_CK can also be stopped during the read wait interval for SD I/O cards: in this case the
SDIO_CLKCR register does not control SDIO_CK.
SDIO argument register (SDIO_ARG)
Address offset: 0x08
Reset value: 0x0000 0000
The SDIO_ARG register contains a 32-bit command argument, which is sent to a card as
part of a command message.
Bit 10 BYPASS: Clock divider bypass enable bit
Bit 9 PWRSAV: Power saving configuration bit
Bit 8 CLKEN: Clock enable bit
Command argument sent to a card as part of a command message. If a command contains
an argument, it must be loaded into this register before writing a command to the command
register.
0: Disable bypass: SDIOCLK is divided according to the CLKDIV value before driving the
SDIO_CK output signal.
1: Enable bypass: SDIOCLK directly drives the SDIO_CK output signal.
For power saving, the SDIO_CK clock output can be disabled when the bus is idle by setting
PWRSAV:
0: SDIO_CK clock is always enabled
1: SDIO_CK is only enabled when the bus is active
0: SDIO_CK is disabled
1: SDIO_CK is enabled
This field defines the divide factor between the input clock (SDIOCLK) and the output clock
(SDIO_CK): SDIO_CK frequency = SDIOCLK / [CLKDIV + 2].
Doc ID 13902 Rev 9
CMDARG
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RM0008
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