MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 39

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
In connectivity line devices the main system consists of:
●
●
These are interconnected using a multilayer AHB bus architecture as shown in
Figure 2.
ICode bus
This bus connects the Instruction bus of the Cortex™-M3 core to the Flash memory
instruction interface. Prefetching is performed on this bus.
Five masters:
–
–
–
Three slaves:
–
–
–
DMA1
DMA2
USB OTG FS
Ethernet MAC
Ch.1
Ch.2
Ch.5
Cortex-M3
Cortex™-M3 core DCode bus (D-bus) and System bus (S-bus)
GP-DMA1 & 2 (general-purpose DMA)
Ethernet DMA
Internal SRAM
Internal Flash memory
AHB to APB bridges (AHB2APBx), which connect all the APB peripherals
Ch.1
Ch.2
Ch.7
System architecture in connectivity line devices
DCode
Sys tem
DMA
Doc ID 13902 Rev 9
ICode
DMA request
AHB system bus
Reset & clock
control (RCC)
FLITF
Bridge 2
Bridge 1
Memory and bus architecture
ADC1
ADC2
USART1
SPI1
TIM1
GPIOA
GPIOB
DMA request
SRAM
GPIOC
GPIOD
GPIOE
APB2
AFIO
EXTI
Flash
DAC
PWR
BKP
CAN1
CAN2
I2C2
I2C1
UART5
UART4
USART3
USART2
Figure
SPI3/I2S
SPI2/I2S
APB 1
WWDG
IWDG
TIM7
TIM6
TIM5
TIM4
TIM3
TIM2
RTC
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