MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 441

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MCBSTM32EXL

Manufacturer Part Number
MCBSTM32EXL
Description
BOARD EVALUATION FOR STM32F103ZE
Manufacturer
Keil
Datasheets

Specifications of MCBSTM32EXL

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
RM0008
19.6
Bits 7:4 ADDHLD: Address-hold phase duration.
Bits 3:0 ADDSET: Address setup phase duration.
NAND Flash/PC Card controller
The FSMC generates the appropriate signal timings to drive the following types of device:
The NAND/PC Card controller can control three external banks. Bank 2 and bank 3 support
NAND Flash devices. Bank 4 supports PC Card devices.
Each bank is configured by means of dedicated registers
programmable memory parameters include access timings (shown in
configuration.
Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always
1 Flash clock period duration.
Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always
1 Flash clock period duration.
These bits are written by software to define the duration of the address hold phase (refer to
Figure 170
accesses:
0000: Reserved
0001: ADDHLD phase duration = 2 × HCLK clock cycle
0010: ADDHLD phase duration = 3 × HCLK clock cycle
...
1111: ADDHLD phase duration = 16 × HCLK clock cycles (default value after reset)
These bits are written by software to define the duration of the address setup phase in HCLK
cycles (refer to
NOR Flash:
0000: ADDSET phase duration = 1 × HCLK clock cycle
...
1111: ADDSET phase duration = 16 × HCLK clock cycles (default value after reset)
NAND Flash
16-bit PC Card compatible devices
8-bit
16-bit
to
Figure
Figure 170
172), used in SRAMs, ROMs and asynchronous multiplexed NOR Flash
to
Figure
Doc ID 13902 Rev 9
172), used in SRAMs, ROMs and asynchronous multiplexed
Flexible static memory controller (FSMC)
(Section
19.6.7). The
Table
113) and ECC
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