MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 638

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Inter-integrated circuit (I
Note:
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corresponding DMA channel is reached, the DMA controller sends an End of Transfer EOT
signal to the I
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●
Transmission using DMA
DMA mode can be enabled for transmission by setting the DMAEN bit in the I2C_CR2
register. Data will be loaded from a Memory area configured using the DMA peripheral (refer
to the DMA specification) to the I2C_DR register whenever the TxE bit is set. To map a DMA
channel for I
When the number of data transfers which has been programmed in the DMA Controller
registers is reached, the DMA controller sends an End of Transfer EOT/ EOT_1 signal to the
I
vector.
Do not enable the ITBUFEN bit in the I2C_CR2 register if DMA is used for transmission.
Reception using DMA
DMA mode can be enabled for reception by setting the DMAEN bit in the I2C_CR2 register.
Data will be loaded from the I2C_DR register to a Memory area configured using the DMA
peripheral (refer to the DMA specification) whenever a data byte is received. To map a DMA
channel for I
1.
2.
3.
4.
5.
6.
2
C interface and the DMA generates an interrupt, if enabled, on the DMA channel interrupt
Master transmitter: In the interrupt routine after the EOT interrupt, disable DMA
requests then wait for a BTF event before programming the Stop condition.
Master receiver: when the number of bytes to be received is equal to or greater than
two, the DMA controller sends a hardware signal, EOT_1, corresponding to the last but
one data byte (number_of_bytes – 1). If, in the I2C_CR2 register, the LAST bit is set,
I
generate a Stop condition in the DMA Transfer Complete interrupt routine if enabled.
Set the I2C_DR register address in DMA_CPARx register. The data will be moved from
this address to the memory after each RxNE event.
Set the memory address in the DMA_CMARx register. The data will be loaded from the
I2C_DR register to this memory area after each RxNE event.
Configure the total number of bytes to be transferred in the DMA_CNDTRx register.
After each RxNE event, this value will be decremented.
Configure the channel priority using the PL[0:1] bits in the DMA_CCRx register
Reset the DIR bit and configure interrupts in the DMA_CCRx register after half transfer
or full transfer depending on application requirements.
Activate the channel by setting the EN bit in the DMA_CCRx register.
2
C automatically sends a NACK after the next byte following EOT_1. The user can
1.Set the I2C_DR register address in the DMA_CPARx register. The data will be
2. Set the memory address in the DMA_CMARx register. The data will be loaded
3. Configure the total number of bytes to be transferred in the DMA_CNDTRx
4. Configure the channel priority using the PL[0:1] bits in the DMA_CCRx register
5. Set the DIR bit and, in the DMA_CCRx register, configure interrupts after half
6. Activate the channel by setting the EN bit in the DMA_CCRx register.
2
2
2
C transmission, perform the following sequence. Here x is the channel number.
2
C reception, perform the following sequence. Here x is the channel number.
C) interface
moved to this address from the memory after each TxE event.
into I2C_DR from this memory after each TxE event.
register. After each TxE event, this value will be decremented.
transfer or full transfer depending on application requirements.
C interface and generates a Transfer Complete interrupt if enabled:
Doc ID 13902 Rev 9
RM0008