MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 794

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

USB on-the-go full-speed (OTG_FS)
26.15.4
794/995
Host programming model
Channel initialization
The application must initialize one or more channels before it can communicate with
connected devices. To initialize and enable a channel, the application must perform the
following steps:
1.
2.
3.
4.
5.
6.
Halting a channel
The application can disable any channel by programming the OTG_FS_HCCHARx register
with the CHDIS and CHENA bits set to 1. This enables the OTG_FS host to flush the posted
requests (if any) and generates a channel halted interrupt. The application must wait for the
CHH interrupt in OTG_FS_HCINTx before reallocating the channel for other transactions.
The OTG_FS host does not interrupt the transaction that has already been started on the
USB.
Before disabling a channel, the application must ensure that there is at least one free space
available in the non-periodic request queue (when disabling a non-periodic channel) or the
periodic request queue (when disabling a periodic channel). The application can simply
flush the posted requests when the Request queue is full (before disabling the channel), by
programming the OTG_FS_HCCHARx register with the CHDIS bit set to 1, and the CHENA
bit cleared to 0.
The application is expected to disable a channel on any of the following conditions:
1.
2.
Program the GINTMSK register to unmask the following:
Channel interrupt
–
–
Program the OTG_FS_HAINTMSK register to unmask the selected channels’
interrupts.
Program the OTG_FS_HCINTMSK register to unmask the transaction-related
interrupts of interest given in the host channel interrupt register.
Program the selected channel’s OTG_FS_HCTSIZx register with the total transfer size,
in bytes, and the expected number of packets, including short packets. The application
must program the PID field with the initial data PID (to be used on the first OUT
transaction or to be expected from the first IN transaction).
Program the OTG_FS_HCCHARx register of the selected channel with the device’s
endpoint characteristics, such as type, speed, direction, and so forth. (The channel can
be enabled by setting the channel enable bit to 1 only when the application is ready to
transmit or receive any packet).
When an XFRC interrupt in OTG_FS_HCINTx is received during a non-periodic IN
transfer or high-bandwidth interrupt IN transfer (Slave mode only)
When an STALL, TXERR, BBERR or DTERR interrupt in OTG_FS_HCINTx is received
for an IN or OUT channel (Slave mode only). For high-bandwidth interrupt INs in Slave
mode, once the application has received a DTERR interrupt it must disable the channel
and wait for a channel halted interrupt. The application must be able to receive other
interrupts (DTERR, Nak, Data, TXERR) for the same channel before receiving the halt.
Non-periodic transmit FIFO empty for OUT transactions (applicable for Slave
mode that operates in pipelined transaction-level with the packet count field
programmed with more than one).
Non-periodic transmit FIFO half-empty for OUT transactions (applicable for Slave
mode that operates in pipelined transaction-level with the packet count field
programmed with more than one).
Doc ID 13902 Rev 9
RM0008