MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 383

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RM0008
15.4.2
15.4.3
15
15
14
14
Bits 15:7 Reserved, always read as 0.
Bit 15:9 Reserved, always read as 0.
Bits 6:4 MMS: Master mode selection
Bits 3:0 Reserved, always read as 0
Bit 7:1 Reserved, always read as 0.
TIM6&TIM7 control register 2 (TIMx_CR2)
Address offset: 0x04
Reset value: 0x0000
TIM6&TIM7 DMA/Interrupt enable register (TIMx_DIER)
Address offset: 0x0C
Reset value: 0x0000
Bit 8 UDE: Update DMA request enable
Bit 0 UIE: Update interrupt enable
13
13
Reserved
0: Update DMA request disabled.
1: Update DMA request enabled.
0: Update interrupt disabled.
1: Update interrupt enabled.
These bits are used to select the information to be sent in master mode to slave timers for
synchronization (TRGO). The combination is as follows:
000: Reset - the UG bit from the TIMx_EGR register is used as a trigger output (TRGO). If
reset is generated by the trigger input (slave mode controller configured in reset mode) then
the signal on TRGO is delayed compared to the actual reset.
001: Enable - the Counter enable signal, CNT_EN, is used as a trigger output (TRGO). It is
useful to start several timers at the same time or to control a window in which a slave timer
is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit
and the trigger input when configured in gated mode.
When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO,
except if the master/slave mode is selected (see the MSM bit description in the TIMx_SMCR
register).
010: Update - The update event is selected as a trigger output (TRGO). For instance a
master timer can then be used as a prescaler for a slave timer.
12
12
Reserved
11
11
10
10
9
9
Doc ID 13902 Rev 9
UDE
rw
8
8
7
7
rw
6
6
MMS[2:0]
rw
5
5
Reserved
rw
4
4
Basic timers (TIM6&TIM7)
3
3
2
2
Reserved
1
1
383/995
UIE
rw
0
0