MCBSTM32EXL Keil, MCBSTM32EXL Datasheet - Page 38

• Manufacturer Part Number: MCBSTM32EXL
• Description: BOARD EVALUATION FOR STM32F103ZE
• Manufacturer: Keil

Specifications of MCBSTM32EXL

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Memory and bus architecture
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2.1
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Memory and bus architecture
System architecture
In low-, medium- and high-density devices, the main system consists of:
●
●
These are interconnected using a multilayer AHB bus architecture as shown in
Figure 1.
DMA1
DMA2
Four masters:
–
–
Four slaves:
–
–
–
–
Ch.1
Ch.2
Ch.5
Cortex-M3
Ch.1
Ch.2
Ch.7
Cortex™-M3 core DCode bus (D-bus) and System bus (S-bus)
GP-DMA1 & 2 (general-purpose DMA)
Internal SRAM
Internal Flash memory
FSMC
AHB to APB bridges (AHB2APBx), which connect all the APB peripherals
System architecture
Sys tem
DCode
DMA
ICode
Doc ID 13902 Rev 9
AHB system bus
Reset & clock
control (RCC)
DMA Request
SDIO
FSMC
FLITF
Bridge 2
Bridge 1
DMA request
ADC3
ADC1
ADC2
USART1
SPI1
TIM1
TIM8
GPIOA
GPIOB
SRAM
GPIOC
GPIOD
GPIOG
GPIOE
GPIOF
APB2
AFIO
EXTI
Flash
DAC
PWR
BKP
bxCAN
USB
I2C2
I2C1
UART5
UART4
USART3
USART2
SPI3/I2S
SPI2/I2S
APB 1
WWDG
IWDG
Figure
TIM4
TIM7
TIM6
TIM5
TIM3
TIM2
RTC
ai14800c
RM0008
1: